Patents Examined by Tahilba O Puche
  • Patent number: 12223205
    Abstract: Disclosed herein are systems, methods and devices for controlling output of a storage device during read operations. The method comprises: measuring a length of a temporal gap between first and second consecutive read bursts from a storage device, the first and second read burst are in response to first and second read commands received by the storage device, respectively; generating a state code according to the length, wherein the state code has a first value when the length is zero, a second value when the length is equal to or shorter than a threshold time length but is non-zero, and a third value when the length is greater than the threshold time length; and controlling output of the storage device according to the state code.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: February 11, 2025
    Assignee: InnoGrit Technologies Co., Ltd.
    Inventors: Hongsen Yu, Shawn Chen, Gang Zhao, Wei Jiang, Lin Chen
  • Patent number: 12210747
    Abstract: A system is described. The system includes a processing resource and a non-transitory computer-readable medium, coupled to the processing resource, having stored therein instructions that when executed by the processing resource cause the processing resource to receive a plurality of quality of service (QoS) parameters and client preferences from a client device and manage a QoS policy based on a plurality of QoS objectives included in the received QoS parameters, wherein the plurality of QoS objectives comprise input output operations per second (IOPS), throughput and latency.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: January 28, 2025
    Assignee: NetApp, Inc
    Inventors: Austino Longo, Tyler Cady
  • Patent number: 12210755
    Abstract: Nodes in a storage system can autonomously ingest I/O requests and flush data to storage. First and second nodes determine a sequence separator, the sequence separator corresponding to an entry in a page descriptor ring that separates two flushing work sets (FWS). The first node receives an input/output (I/O) request and allocates a sequence identification (ID) number to the I/O request. The first node determines a FWS for the I/O request based on the sequence separator and the sequence ID number, and commits the I/O request using the sequence ID number. The I/O request and the sequence ID number are sent to the second node.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: January 28, 2025
    Assignee: Dell Products L.P.
    Inventors: Vladimir Shveidel, Geng Han, Yousheng Liu
  • Patent number: 12210753
    Abstract: Systems, apparatus and methods are provided for determining an optimal performance profile and a predicted temperature. A method may include receiving a command from a host. The command may contain a logical block address (LBA) for data stored in a data storage system, a length for a data size associated with the command, and a timestamp associated with the command. The method may further include obtaining LBA information, the timestamp, the data size from the command, providing the LBA information, the timestamp, the data size, along with temperature readings, and a performance profile as inputs to a machine learning model, determining an optimal performance profile and a predicted temperature using the machine learning model and configuring a storage controller with settings of the optimal performance profile.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: January 28, 2025
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Gang Zhao, Lin Chen
  • Patent number: 12197748
    Abstract: A storage device includes a memory device including user memory blocks providing a user data region; and a controller configured to: map logical addresses used in a host to a portion of the user data region, and use a remaining portion of the user data region as an over-provisioning region, wherein the controller is further configured to control the memory device to: erase the user memory blocks based on a sanitize command from the host, provide, to the host, block address information of the user memory blocks based on a block address request from the host, access the user memory blocks based on block state check requests from the host, and provide, to the host, state information indicating whether the user memory blocks are erased according to access results.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: January 14, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younghyun Ji, Jisoo Kim, Kyungwoo Noh, Kyungjin Lee
  • Patent number: 12197735
    Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: January 14, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
  • Patent number: 12189961
    Abstract: A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: January 7, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yu-Chung Lien, Zhenming Zhou
  • Patent number: 12164796
    Abstract: Various implementations described herein relate to systems and methods for transferring data from a source device to a destination device including receiving, by the destination device, a copy request from a host, performing, by the destination device, transfer with the source device to transfer data from buffers of the source device to buffers of the destination device, and writing, by the destination device, the data to a non-volatile storage of the destination device.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 10, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Krishna Malakapalli, Jeremy Werner, Kenichi Iwai
  • Patent number: 12164770
    Abstract: Techniques for processing a read I/O operation directed to a logical address LA1 can include: determining a logical address range R1 including LA1; determining whether a unified cache includes a cached object corresponding to R1; and responsive to determining that the unified cache does not include a cached object corresponding to R1, determining a unified cache miss with respect to R1 and performing unified cache miss processing including: traversing metadata pages, including a metadata leaf page, corresponding to LA1; storing indirect pointers from entries of the metadata leaf page to corresponding entries of a new metadata leaf object of the unified cache corresponding to R1; performing processing using an indirect pointer of an entry of the new metadata leaf object, where the entry corresponds to LA1 and the processing includes retrieving the content of LA1 using the indirect pointer; and returning the content in response to the read I/O operation.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: December 10, 2024
    Assignee: Dell Products L.P.
    Inventors: Vladimir Shveidel, Vamsi K Vankamamidi, Amitai Alkalay
  • Patent number: 12158841
    Abstract: The present invention provides a control method of a flash memory controller is disclosed, wherein the flash memory controller is configured to access a flash memory module, and the control method comprising: allocating a memory space within a memory for storing data from the host device; dividing the memory space into a plurality of zone buffers, wherein each of the zone buffers is used to store data corresponding to one zone having an opened state; and for a first zone buffer of the plurality of zone buffers, controlling a first buffer and a second buffer within the first zone buffer to alternately store data of a first zone from the host device and write the data of the first zone to a zoned namespace of the flash memory module.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: December 3, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Kun-Cheng Lai, Yen-Yu Jou
  • Patent number: 12153519
    Abstract: Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: November 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Patent number: 12094565
    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: September 17, 2024
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 12045467
    Abstract: Exemplary methods, apparatuses, and systems including a quality-of-service (QoS) processor for managing performance of a memory device. The QoS processor negotiates a configuration policy with one or more hosts. The QoS processor communicates the configuration policy to a memory device. The QoS processor monitors a workload of the memory device, the workload including one or more requests from the one or more hosts for the memory device to perform a type of computing operation. The QoS processor classifies the workload by comparing the workload to execution parameters of the memory device. The QoS processor computes a projected QoS using the classification of the workload. The QoS processor updates the configuration policy using the projected QoS.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: July 23, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Manjunath Chandrashekaraiah
  • Patent number: 12045173
    Abstract: Aspects of the present invention disclose a method, computer program product, and system for stale data recovery using virtual storage metadata. The method includes one or more processors generating a primary virtual storage metadata structure having virtual address areas for a data chunk. Each area includes a plurality of most recent updates of metadata for the data chunk. The metadata of each update includes a sequence number for the update and a pointer to the physical location of the data. The method further includes one or more processors generating an overflow virtual storage metadata structure for multiple virtual address areas. The overflow metadata structure includes updates that have overflowed from the virtual address areas. In addition, wherein an oldest update in a full virtual address area of the primary virtual storage metadata structure includes a link to an overflow location.
    Type: Grant
    Filed: April 18, 2020
    Date of Patent: July 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ben Sasson, Gordon Douglas Hutchison, Lee Jason Sanders, Gareth Paul Jones
  • Patent number: 12045490
    Abstract: Disclosed herein are system, method, and computer program product embodiments for managing data storage devices. In some embodiments, a server receives a request to store data in a first storage device. The server determines the storage space remaining in the first data storage device based on historical data associated with the first data storage device. The server further determines that the first data storage device will exceed its storage capacity based on a size of the data and the storage space remaining in the first data storage device. The server transfers a set of data stored in the first data storage device to a second storage device. Transferring the set of data causes the storage space remaining in the first storage device to be greater than or equal to the size of the data. The server stores the data in the first data storage device.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: July 23, 2024
    Assignee: SAP SE
    Inventors: Sreenivasulu Gelle, Alexander Ocher
  • Patent number: 12014065
    Abstract: Multi-cloud orchestration as a service, including: receiving a provisioning request for one or more cloud computing resources; identifying, based on a first one or more metrics, a particular cloud computing environment from a plurality of cloud computing environments to satisfy the provisioning request; and provisioning, in the particular cloud computing environment, the one or more cloud computing resources.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: June 18, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: David Whitlock, Argenis Fernandez
  • Patent number: 11983438
    Abstract: A technique improves implementation of an index for an operations log (oplog) that coalesces random write operations directed to a virtual disk (vdisk) stored on an extent store. The oplog temporarily caches data associated with the random write operations (i.e., write data) as well as metadata describing the write data. The metadata includes descriptors to the write data stored on virtual address regions, i.e., offset ranges, of the vdisk and are used to identify the offset ranges of write data for the vdisk that are cached in the oplog. To facilitate fast lookup operations of the offset ranges when determining whether write data is cached in the oplog, an oplog index provides a state of the latest data for offset ranges of the vdisk. The technique improves implementation of the oplog index by storing the oplog index in storage class memory, such as persistent memory, to obviate failure and subsequent recovery of the oplog index.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 14, 2024
    Assignee: Nutanix, Inc.
    Inventors: Alok Nemchand Kataria, Niranjan Sanjiv Pendharkar, Pete Wyckoff, Shubham Shukla, Tabrez Parvez Memon
  • Patent number: 11966583
    Abstract: The present disclosure provides a data pre-processing method and device and related computer device and storage medium. By storing the target output data corresponding to the target operation into the first memory close to the processor and reducing the time of reading the target output data, the occupation time of I/O read operations during the operation process can be reduced, and the speed and efficiency of the processor can be improved.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 23, 2024
    Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Shaoli Liu, Xiaofu Meng
  • Patent number: 11966584
    Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for managing a storage device. The method includes: determining, based on the frequency of data access to the storage device, whether a data access component of the storage device will move; determining, if it is determined that the data access component will move, a first storage unit in the storage device based on a storage location of previously accessed data in the storage device, wherein the data access component is located at a first spatial location corresponding to the first storage unit; and sending a read request for data in a second storage unit in the storage device that is adjacent to the first storage unit, so as to cause the data access component to move from the first spatial location to a second spatial location corresponding to the second storage unit. The embodiments of the present disclosure can reduce the latency of data access to the storage device.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: April 23, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Bing Liu, Zheng Li
  • Patent number: 11960726
    Abstract: A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 16, 2024
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Yiren Huang, Yong Wang, Kui (Kevin) Lin