Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract: A method for automatically configuring a PCIe slot comprises: writing a configuration value into a storage device, with the configuration value associated with a configuration manner of the PCIE slot, reading the configuration value from the storage device by a BIOS, and determining whether the configuration value belongs to a valid value set, the BIOS configures a data bandwidth of the PCIe slot according to the configuration value when the configuration value belongs to a valid value set, and the BIOS configures the data bandwidth of the PCIe slot according to a default value when the configuration values does not belong to the valid value set.

Abstract: A method for performing configuration management, an associated data storage device and the controller thereof are provided. The method may include: reading a read-only memory (ROM) code from a ROM to execute the ROM code; during executing the ROM code, detecting a first set of states of a general-purpose input/output (GPIO) circuit to perform a first portion of system configuration settings of the ROM code according to the first set of states; during executing the ROM code, detecting a second set of states of an electronic fuse (eFuse) circuit to perform a second portion of system configuration settings of the ROM code according to the second set of states; and executing at least one program code to make the data storage device be ready for being accessed by a host device.

Abstract: A computer-implemented method according to one embodiment includes creating a single data log; storing data from a plurality of different data streams in at least one data unit of the single data log; and allocating an additional data unit to the single data log in response to one or more criteria.

Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing security settings for calls from predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a call to execute a routine identified using the virtual memory address, a security setting corresponding to the execution domain from which the call initiates can be extracted from the page table entry to determine whether a security measure is to be used. For example, a shadow stack structure can be used to protect the private stack content of the routine from being access by a caller and/or to protect the private stack content of the caller from being access by the callee.

Abstract: An information processing system equipped with an information processing device, which includes multiple processors and a common parallel port (port), and a peripheral device, which includes a data classification means and multiple computing means. Each processor appends each processor identifier to a respective series of codes capable of expressing given data, thereby generating a writing unit capable of being written one time in the bus width of the port, and sequentially writes the writing unit to the port without performing exclusive control. A data classification means reads the writing units from the port sequentially and sequentially outputs the series of codes included in the writing unit to a computing means associated with the processor identifiers included in the writing unit. The computing means reconstructs the original data on the basis of the series of codes.

Abstract: The invention introduces a method for executing host input-output (IO) commands, performed by a processing unit of a device side when loading and executing program code of a first layer, at least including: receiving a host IO command from a host side through a frontend interface; generating a slot bit table (SBT) including an entry according to the host IO command; creating a thread of a second layer; and sending addresses of callback functions and the SBT to the thread of the second layer, thereby enabling the thread of the second layer to call the callback functions according to the IO operation of the SBT for driving the frontend interface to interact with the host side to transmit user data read from a storage unit to the host side, or receive user data to be programmed into the storage unit from the host side.

Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.

Abstract: Reads of data stored at the solid-state storage device are monitored. A set of data stored at the solid-state storage device is marked based on the monitoring of the reads of the data. A read request is received for a subset of data of the set of data stored at the storage device. In response to receiving the read request for the subset of data, the subset of data is relocated to a cache memory of the solid-state storage device.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

Abstract: A method is disclosed for dynamic multitasking in a storage system, the storage system including a first storage server configured to execute a first I/O service process and one or more second storage servers, the method comprising: detecting a first event for triggering a context switch; transmitting to each of the second storage servers an instruction to stop transmitting internal I/O requests to the first I/O service process, the instruction including an identifier corresponding to the first I/O service process, the identifier being arranged to distinguish the first I/O service process from other first I/O service processes that are executed by the first storage server concurrently with the first I/O service process; deactivating the first I/O service process by pausing a frontend of the first I/O service process, and pausing one or more I/O providers of the first I/O service process; and executing a first context switch between the first I/O service process and a second process.

Abstract: Systems, apparatuses, and methods related to a domain register of a processor in a computer system are described. The computer system has a memory configured to at least store instructions of routines that are classified in multiple predefined, non-hierarchical domains. The processor stores in the domain register an identifier of a current domain of a routine that is being executed in the processor. The processor is configured to perform security operations based on the content of the domain register and the security settings specified respectively for the predefined, non-hierarchical domains.

Abstract: An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.

Abstract: A wearable device is disclosed. In one embodiment, the device includes: a sensor array having a plurality of sensors each detecting a physical change in epidermis of a corresponding body area and a body movement determination unit configured to determine movement of a body part based on sensing signals respectively received from the plurality of sensors.

Abstract: Disclosed is an electronic apparatus comprising: a plurality of connectors to which a plurality of function modules is mountable; a host device configured to make a request for information to the plurality of function modules mounted to the connector, identify suitability of the plurality of function modules according to a function and priority based on the information received from the plurality of function modules, and control the function module to perform a specific function when the function module essentially required for the specific function is fully mounted.

Abstract: In an embodiment of the invention, a method comprises: A method, comprising: issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table.

Abstract: One or more storage systems are connected to one or more storage boxes comprising multiple storage devices. Multiple storage areas provided by one or more storage boxes include an allocated area, which is a storage area that is allocated to a virtual volume, and an empty area, which is a storage area that is not allocated to any logical volume. Multiple owner rights corresponding to multiple storage areas are set in one or more storage systems. A storage system having an empty area owner right changes an empty area to the allocated area by allocating the empty area. In a case where a configuration change (a relative change in the number of storage boxes with respect to the number of storage systems) is performed, a first storage system that exists after the configuration change sets, in the first storage system, either more or fewer owner rights than the owner rights, which have been allocated to the first storage system before the configuration change.

Abstract: A control device receives a first request signal for requesting to write first data in a first logical address area of a logical volume set stores the first data in a physical volume in accordance with the first request signal, erases, after receiving the first request signal, the first data in the first logical address area of the logical volume without erasing the first data in the physical volume, and when executing a first erasure processing for erasing the first data in the physical volume, holds the first data in the physical volume, in a case where history information for indicating that a second erasure processing has been executed prior to the first erasure processing is held, and erases the first data in the physical volume, in a case where the history information is not held.