Abstract: A data processing system includes a host processor, a processor suitable for processing a task instructed by the host processor, a memory, shared by the host processor and the processor, that is suitable for storing data processed by the host processor and the processor, respectively, and a memory controller suitable for checking whether a stored data processed by the host processor and the processor are reused, and for sorting and managing the stored data as a first data and a second data based on the check result.
Abstract: A storage device configured for connection with a host includes; an output unit configured to provide at least one storage device operating state indication to a user, an input unit configured to accept at least one user input, a main memory configured to temporarily store data received from the host, a storage configured to store the data in non-volatile memory space, and a controller configured to execute a backup operation in response to a user input accepted by the input unit, transfer data from the main memory to the storage during the backup operation, and provide a storage device operating state indication through the output unit during execution of the backup operation.
Abstract: Data compression is performed on a storage system for which one or more host systems have direct access to data on the storage system. The storage system may compress the data for one or more logical storage units (LSUs) having data stored thereon, and may update compression metadata associated with the LSUs and/or the data portions thereof to reflect that the data is compressed. In response to a read request for a data portion received from a host application executing on the host system, compression metadata for the data portion may be accessed. If it is determined from the compression metadata that the data portion is compressed, the data compression metadata for the data portion may be further analyzed to determine how to decompress the data portion. The data portion may be retrieved and decompressed, and the decompressed data may be returned to the requesting application.
Type:
Grant
Filed:
January 15, 2020
Date of Patent:
April 5, 2022
Assignee:
EMC IP Holding Company LLC
Inventors:
Ian Wigmore, Gabriel Benhanokh, Arieh Don, Alesia A. Tringale
Abstract: An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.
Abstract: A method for changing over a general-purpose OS display for an information processing apparatus to a dedicated display screen includes accessing a setup procedure describing setup processing and at least an account generating process for generating user account information for a general-purpose operating system (“OS”). The method includes accessing changeover information for changing over a general-purpose OS display screen for the information processing apparatus to a dedicated display screen, and in response to starting up the general-purpose OS for the first time, executing the setup processing including the user account generating process based on the setup procedure stored by the procedure storage unit, changing over the general-purpose OS display screen to the dedicated display screen based on the changeover information stored by the changeover information storage unit, and displaying the dedicated display screen. An apparatus and a program product perform the method.
Abstract: Embodiments of the present disclosure relate to a method, a device and a computer program product for managing backup data. The method comprises receiving a first request from a user for managing backup data on a first virtual machine management platform. The method further comprises sending a second request comprising a user identifier and a platform identifier to a backup server. The method further comprises receiving, from the backup server, a first virtual machine identifier of the first virtual machine used by the user on the second virtual machine management platform and backup records corresponding to the first virtual machine identifier. The method further comprises determining, based on the first virtual machine identifier, whether a second virtual machine matched with the first virtual machine is present in the first virtual machine management platform.
Type:
Grant
Filed:
December 23, 2019
Date of Patent:
April 5, 2022
Assignee:
EMC IP HOLDING COMPANY LLC
Inventors:
Phoenix Yun Wang, Rita Na Li, Bing Bai, Eric Qiang Ye, Jing Wang
Abstract: Embodiments of the present description provide a data processing method and apparatus, and an edge device. A currently received message is written to a first area of a local disk, and upon writing the currently received message to the first area of the local disk, the currently received message is buffered to a cache. When an edge device is restarted, data in the cache may be restored according to data stored in the first area of the local disk.
Abstract: Systems, apparatuses, and methods related to image based media type selection are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile). Determinations of which memory media types to write image data to can be made and the data can be written (e.g., stored) in the determined type of memory media. A determined memory media type can be based on attributes of the data. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, initial image data from an image sensor coupled to the memory system, identifying one or more attributes of the initial image data, determining a type of memory media to write the initial image data to based on the identified attributes of the initial image data, and selecting, based at least in part on the determined type of memory media, a first memory type of the plurality of memory media types to write the initial image data.
Type:
Grant
Filed:
March 2, 2020
Date of Patent:
March 15, 2022
Assignee:
Micron Technology, Inc.
Inventors:
Carla L. Christensen, Zahra Hosseinimakarem, Bhumika Chhabra
Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
Abstract: The invention provides a data storage device comprising a controller and a data storage unit. The data storage unit comprises a first system storage area and a second system storage area. The first system storage area stores an original operating system, and comprises a first initial sector address. The second system storage area stores a backup operating system, and comprises a second initial sector address. The controller comprises a firmware. A boot pointer offset procedure is defined in the firmware. A boot pointer is preset by the firmware to point to the first initial sector address of the first system storage area, and therefore a boot operation is executed by the original operating system. When the original operating system damages, the firmware executes the boot pointer offset procedure to offset the boot pointer to the second initial sector address, and executes the boot operation by the backup operating system.
Abstract: A processing device in a memory system receives a privilege key from a host system, the privilege key having an associated level of access to debug information associated with the memory device and determines the level of access associated with the privilege key. The processing device receives, from the host system, a request for debug information directed to a debug slave address associated with a system management bus port of a memory sub-system, identifies the debug information corresponding to the level of access associated with the privilege key, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.
Type:
Grant
Filed:
May 14, 2020
Date of Patent:
March 8, 2022
Assignee:
MICRON TECHNOLOGY, INC.
Inventors:
Joe Mendes, Chandra M. Guda, Steven Gaskill
Abstract: A medical system includes an input assembly for receiving one or more user inputs. The input assembly includes at least one slider assembly for providing an input signal. Processing logic receives the input signal from the input assembly and provides a first output signal and a second output signal. A display assembly is configured to receive, at least in part, the first output signal from the processing logic and render information viewable by the user. The second output signal is provided to one or more medical system components. The information rendered on the display assembly may be manipulatable by the user and at least a portion of the information rendered may be magnified.
Type:
Grant
Filed:
September 4, 2020
Date of Patent:
February 15, 2022
Assignee:
DEKA PRODUCTS LIMITED PARTNERSHIP
Inventors:
Kevin L. Grant, Douglas J. Young, Matthew C. Harris
Abstract: A method for configuring a set of one or more computing devices, includes generating, for a computing device of the set of one or more computing devices, a job profile based at least in part on a master profile, the master profile being generated based at least in part on configuration information common to a model of the computing device and job specific input including configuration information specific to the computing device of the set of one or more computing devices. The method further includes coupling the computing device of the set of one or more computing devices into communication with a pre-configuration device; and configuring, by the pre-configuration device, the computing device of the set of one or more computing devices based at least in part on the generated job profile.
Abstract: The present disclosure discloses a parameter configuration method and apparatus, and a display device, belonging to the field of display technologies. The method is applicable to a controller connected to a plurality of drivers, and includes: sending a component information request instruction to a first driver over a first signal line, wherein the first driver is one of the plurality of drivers; receiving a component information response instruction sent over the first signal line by the first driver, wherein the component information response instruction includes component information; determining configuration parameters corresponding to the component information; and performing parameter configuration for the plurality of drivers by using the determined configuration parameters.
Abstract: The embodiments of the present disclosure disclose a firmware boot implementation method based on Flash chip simulation, the method comprising: when there are at least two MCUs, one of the MCUs is selected as a master MCU and each remaining MCU is as slave MCU which is connected with the master MCU respectively, and the master MCU is connected with a Flash chip; when the master MCU is started, the master MCU is started by reading firmware data in the Flash chip; when the slave MCU is started, the master MCU controls the slave MCU to be powered on, and the slave MCU sends a request for reading the firmware data to the master MCU; the master MCU transmits the request to the Flash chip, and transmits the firmware data returned by the Flash chip to the slave MCU, so as to start the slave MCU.
Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.
Abstract: The invention introduces a method for programming data of page groups into flash units to include steps for: obtaining, by a host interface (I/F) controller, user data of a page group from a host side, wherein the page group comprises multiple pages; storing, by the host I/F controller, the user data on the pages in a random access memory (RAM) through a bus architecture, outputting the user data on the pages to an engine via an I/F, and enabling the engine to calculate a parity of the page group according to the user data on the pages; obtaining, by a direct memory access (DMA) controller, the parity of the page group from the engine and storing the parity of the page group in the RAM through the bus architecture; and obtaining, by a flash I/F controller, the user data on the pages and the parity of the page group from the RAM through the bus architecture, and programming the user data on the pages and the parity of the page group into a flash module.
Abstract: A computer-implemented method at a data management system comprises: retrieving start and end times of a backup of a database; retrieving time stamps of log backups of the database; retrieving sequence numbers of the log backups; generating a graphical user interface illustrating a timeline of availability of database restoration and unavailability; making a second backup of the database; illustrating, on the graphical user interface during the making, pending availability of the second database backup; receiving a command to restore the database at an available time as illustrated by the graphical user interface; and restoring the database.
Type:
Grant
Filed:
May 13, 2020
Date of Patent:
January 4, 2022
Assignee:
RUBRIK, INC.
Inventors:
Deepti Kochar, Snehal Arvind Khandkar, Kevin Rui Luo, Yanzhe Wang
Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
Type:
Grant
Filed:
April 22, 2020
Date of Patent:
January 4, 2022
Assignee:
Micron Technology, Inc.
Inventors:
Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
Abstract: A controller may control a memory device including memory blocks. The controller may include a processor configured to generate a command queue in response to a write command, a wear level management block configured to check a wear level of each memory block based on an erase/program pulse count variation, and manage the memory blocks such that each memory block belong to an SLC memory block group or an MLC memory block group, and a memory device control circuit configured to control the memory device to perform a write operation in response to the command queue. The memory device control circuit may select a first memory block belong to the SLC memory block group when the write operation is an operation for important data, and select a second memory block belong to the MLC memory block group when the write operation is an operation for normal data.