Patents Examined by Tan T. Nguyen
  • Patent number: 11127897
    Abstract: A nonvolatile memory cell includes a semiconductor layer including a first recess and a second recess. A first gate insulation layer is disposed on a bottom surface and side surfaces of the first recess. A second gate insulation layer is disposed on a bottom surface and side surfaces of the second recess. A variable resistive material layer is disposed on a first region of the semiconductor layer disposed between the first and second recesses. An insulation barrier layer disposed on a top surface and side surfaces of the variable resistive material layer. A gate electrode surrounding the insulation barrier layer and extending to fill the first and second recesses.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 21, 2021
    Assignees: SK hynix Inc.
    Inventor: Sang Min Lee
  • Patent number: 11127474
    Abstract: A memory device includes a charge pump connected to a power supply voltage and including a plurality of stages to output an output voltage, a stage counter configured to output a count value that incrementally increases to a number of the stages, and a regulator configured to compare the output voltage with a reference output voltage of the charge pump that is generated using the incrementally increasing count value obtained by the stage counter, and to output a pump operation signal at a time when the reference output voltage becomes greater than or equal to the output voltage, wherein the charge pump operates in response to the pump operation signal.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bilal Ahmad Janjua, Sung Whan Seo
  • Patent number: 11120858
    Abstract: A magnetic memory according to an embodiment includes: a first wiring; a second wiring; a first switching element disposed between the first wiring and the second wiring; a first magnetic member extending in a first direction and disposed between the first switching element and the second wiring; a third wiring disposed between the first magnetic member and the second wiring; a first magnetoresistive element disposed between the third wiring and the second wiring; and a second switching element disposed between the first magnetoresistive element and the second wiring.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 14, 2021
    Assignee: Kioxia Corporation
    Inventors: Yoshihiro Ueda, Michael Arnaud Quinsat
  • Patent number: 11121309
    Abstract: A magnetic memory device may include a perpendicular magnetic structure, an in-plane magnetic structure, a free magnetic pattern between the perpendicular magnetic structure and the in-plane magnetic structure, and a tunnel barrier pattern between the perpendicular magnetic structure and the free magnetic pattern. The perpendicular magnetic structure may include at least one pinned pattern which has a perpendicular magnetization direction that is pinned to a specific direction, and the free magnetic pattern may have a switchable perpendicular magnetization direction. The in-plane magnetic structure may include a first magnetic pattern and a second magnetic pattern, and each of the first and second magnetic patterns may have a different respective in-plane magnetization direction.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: September 14, 2021
    Inventors: Sung Chul Lee, Kwang Seok Kim, Jangeun Lee, Ung Hwan Pi
  • Patent number: 11114148
    Abstract: A wordline driver may include the following: a first transistor having a first node at the input and a second node at an input voltage; a second transistor having a first node at the input node, a second node at a third node of the first transistor, and a third node at ground; a third transistor having a first node at the input voltage, a second node at the first internal node and a third node at a second internal node; a fourth transistor having a first node at an internal node, a second node at a boosted voltage, and a third node at a wordline; a fifth transistor having a first node at an internal node, a second node at the wordline, and a third node at ground; and a sixth transistor between the wordline, the boosted voltage, and the second internal node.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: September 7, 2021
    Assignee: WUXI PETABYTE TECHNOLOGIES CO., LTD.
    Inventor: Feng Pan
  • Patent number: 11107515
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 11107536
    Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
  • Patent number: 11101291
    Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: August 24, 2021
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventors: Menno Mennenga, Johannes Ocker
  • Patent number: 11101009
    Abstract: A memory system is configured to convert multiple programmable memory or a portion thereof to one-time programmable (OTP) memory. The system is configured to repetitively perform memory operations (such as program and erase procedures) on a portion of memory in order to induce accelerated degradation (aging) of select memory cells, thereby permanently changing the select cells, such that a pattern of the cells with degraded performance indicate a data value that has been permanently encoded into the memory.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: August 24, 2021
    Assignee: Board of Trustees of the University of Alabama, for and on behalf of the University of Alabama in Huntsville
    Inventor: Biswajit Ray
  • Patent number: 11094376
    Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Anuj Grover, Tanmoy Roy, Nitin Chawla
  • Patent number: 11087835
    Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Simon J. Lovett
  • Patent number: 11087847
    Abstract: In one example, a nonvolatile memory device, such as a NAND flash memory device, includes an array of non-volatile memory cells. Program operations performed by the memory may be suspended (e.g., in order to service a high priority read request). The memory device includes a timer to track a duration of time the program operation is suspended. Upon program resume, the controller applies a program voltage after resume that is adjusted based on the duration of time the program operation is suspended.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Giacomo Donati, Andrea D'Alessandro, Violante Moschiano
  • Patent number: 11088170
    Abstract: A ferroelectric field effect transistor (FeFET) includes a semiconductor channel, a source region contacting one end of the semiconductor channel, a drain region contacting a second end of the semiconductor channel, a gate electrode, a ferroelectric gate dielectric layer located between the semiconductor channel and the gate electrode, and a bidirectional selector material layer located between the gate electrode and the ferroelectric gate dielectric layer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 10, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Patent number: 11088153
    Abstract: Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Debra M. Bell
  • Patent number: 11087811
    Abstract: An analog Magnetoresistive Random Access Memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction and a domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetically pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetically pinned layer. The analog MRAM cell additionally includes an electrode located adjacent to the magnetic free layer configured to generate heat by supplying current to decrease a conductance of the magnetic free layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Akiyo Iwashina, Atsuya Okazaki, Takeo Yasuda
  • Patent number: 11081523
    Abstract: A memory device may be provided, including a base layer, an insulating layer, a first electrode, a switching element, a capping element and a second electrode. The insulating layer may be arranged over the base layer and may include a recess having opposing side walls. The first electrode may be arranged at least partially within the recess of the insulating layer and along the opposing side walls of the recess of the insulating layer. The switching element may be arranged at least partially within the recess of the insulating layer and along the first electrode. The capping element and the second electrode may be arranged at least partially within the recess of the insulating layer. The capping element may be arranged between the second electrode and the switching element, and a part of the second electrode may extend across the capping element to contact the switching element.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 3, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Yi Jiang, Wanbing Yi, Juan Boon Tan
  • Patent number: 11074962
    Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Takanori Matsuzaki, Kiyoshi Kato, Shunpei Yamazaki
  • Patent number: 11069401
    Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuhsiang Chen, Shao-Yu Chou, Chun-Hao Chang, Min-Shin Wu, Yu-Der Chih
  • Patent number: 11062772
    Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 13, 2021
    Assignee: PANASONIC CORPORATION
    Inventors: Reiji Mochida, Kazuyuki Kouno, Takashi Ono, Masayoshi Nakayama, Yuriko Hayata
  • Patent number: 11056175
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, word lines and bit lines. The semiconductor substrate has active regions separated from one another and extending along a first direction. The word lines are formed in the semiconductor substrate. The active regions are respectively intersected with one or more of the word lines. The word lines respectively have thick portions and a narrow portion continuously extending on the thick portions along a second direction. The thick portions are located at where the word lines are intersected with the active regions. The bit lines are formed over the semiconductor substrate, and extending along a third direction intersected with the first and second directions.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 6, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Noriaki Ikeda