Patents Examined by Tan T. Nguyen
  • Patent number: 11443830
    Abstract: A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a first data structure mapping block identifiers to corresponding block family identifiers, a block family associated with the block of the memory device, determining, using a second data structure mapping block family identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block family, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device, and reading, using the determined set of read levels, data from the block of the memory device.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: September 13, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Shane Nowell, Mustafa N Kaynak, Larry J Koudele
  • Patent number: 11443787
    Abstract: A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region, a second region adjacent to the first region in the first direction, and a third region configured to connect the first region and the second region. The memory cell array further includes: a first insulating layer buried in a first trench between the first region and the second region and in contact with the third region; a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and a first interconnect configured to connect a selection gate line and the first contact plug.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: September 13, 2022
    Assignee: Kioxia Corporation
    Inventor: Takuya Futatsuyama
  • Patent number: 11443810
    Abstract: A negative level shifter includes a shifting circuit and a latch circuit. The shifting circuit shifts levels of a first input signal and a second input signal to provide a first output signal and a second output signal having complementary levels at a first output node and a second output node, respectively, using low voltage transistors and high voltage transistors having different characteristics. The latch circuit, connected to the shifting circuit at the first output node and the second output node, latches the first output signal and the second output signal, receives a negative voltage having a level smaller than a ground voltage, and drives the second output signal and the first output signal complementarily to either a level of a power supply voltage or a level of the negative voltage, based on voltage levels at the first output node and the second output node, respectively.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: September 13, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sooyeol Yang, Hyunggon Kim, Youngsun Song
  • Patent number: 11443803
    Abstract: A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jau-Yi Wu, Win-San Khwa, Jin Cai, Yu-Sheng Chen
  • Patent number: 11437402
    Abstract: A memory cell circuit is provided that may include: a memory cell, the memory cell including a ferroelectric structure; a first control terminal and a second control terminal connected to the memory cell, the first control terminal and the second control terminal being configured to allow an operation of the memory cell; and a first auxiliary terminal and a second auxiliary terminal connected to the memory cell, the first auxiliary terminal and the second auxiliary terminal being configured to provide an auxiliary voltage to the ferroelectric structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: September 6, 2022
    Assignee: Ferroelectric Memory GmbH
    Inventor: Marko Noack
  • Patent number: 11437083
    Abstract: A magnetoresistive random-access memory (MRAM) device includes a first cell selectively connected to a first bit line and a second cell selectively connected to a second bit line. The MRAM device further includes a shared transistor connected to the first cell and connected to the second cell. The MRAM device further includes a first selector device and a second selector device. The first selector device is configured to permit current to flow through the first cell to the shared transistor when a voltage applied to the first selector device is larger than a threshold activation voltage. The second selector device is configured to permit current to flow through the second cell to the shared transistor when a voltage applied to the second selector device is larger than a threshold activation voltage. The MRAM cell further includes a word line connected to a gate of the shared transistor.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: September 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Eric Raymond Evarts
  • Patent number: 11430802
    Abstract: A nonvolatile memory device includes bitlines, a source line, cell channel structures, a gate electrode structure, erase channel structures and an erase selection line. The bitlines are disposed at a first end portion of a cell region, arranged in a first horizontal direction and extend in a second horizontal direction. The source line is disposed at a second end portion of the cell region and extend in the second horizontal direction. The cell channel structures are disposed in a cell string area of the cell region and are respectively connected between the bitlines and the source line. The erase channel structures are disposed in a contact area of the cell region and respectively connected between the bitlines and the source line. The erase channel structures include erase transistors. The erase selection line is disposed in the contact area to form a gate electrode of the erase transistors.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: August 30, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chanho Kim
  • Patent number: 11430510
    Abstract: A device comprises a non-volatile memory and a control system. The non-volatile memory includes an array of non-volatile memory cells, wherein at least one non-volatile memory cell includes a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes first and second source/drain regions, and a gate structure which comprises a ferroelectric layer, and a gate electrode disposed over the ferroelectric layer. The ferroelectric layer comprises a first region adjacent to the first source/drain region and a second region adjacent to the second source/drain region. The control system is operatively coupled to the non-volatile memory to program the FeFET device to have a logic state among a plurality of different logic states. At least one logic state among the plurality of different logic states corresponds to a polarization state of the FeFET device in which the first and second regions of the ferroelectric layer have respective remnant polarizations with opposite polarities.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 30, 2022
    Assignee: International Business Machines Corporation
    Inventors: Nanbo Gong, Takashi Ando, Guy M. Cohen
  • Patent number: 11430527
    Abstract: A method for performing an operation in a memory device is provided. The method includes the following steps. An erasing operation is performed on one selected word line of the memory device to ensure that a plurality of first cells to be programed and a plurality of second cells to be erased connected to the selected word line have threshold voltages lower than a first predetermined level. A programming operation is performed on the selected word line, such that the first cells are suffered a first program bias and the second cells are suffered a second program bias which is lower than the first program bias.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: August 30, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Tzu-Hsuan Hsu
  • Patent number: 11430500
    Abstract: A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Haruka Sakuma, Kiwamu Sakuma, Masumi Saitoh
  • Patent number: 11424251
    Abstract: A semiconductor device is provided. The semiconductor device includes power supply lines extending in a first direction; first transistors, each of which is formed in a first region and has a first threshold voltage; and second transistors, each of which is formed in a second region and has a second threshold voltage higher than the first threshold voltage. One of the plurality of power supply lines is interposed between the first region and the second region, the first transistors implement a first portion of a multiplexer, a clock buffer and a first latch that are disposed on a data path, the second transistors implement a second portion of the multiplexer circuit and a second latch that are disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed in a common location along the first direction.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byounggon Kang, Taejun Yoo, Seunghyun Yang, Dalhee Lee
  • Patent number: 11410721
    Abstract: A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Atsushi Kawasumi
  • Patent number: 11410710
    Abstract: A semiconductor memory device includes a substrate; a first impurity region of a first conductive type; a second impurity region of the first conductivity type apart from the first impurity region in a first direction; a first transistor including a first electrode disposed between the first impurity region and the second impurity region; a third impurity region of the first conductive type apart from the first impurity region in a second direction that crosses the first direction; a fourth impurity region of the first conductive type apart from the third impurity region in the first direction; a second transistor including a second electrode disposed between the third impurity region and the fourth impurity region. The semiconductor memory device includes an active region of the first conductive type between the first transistor and the second transistor.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: August 9, 2022
    Assignee: Kioxia Corporation
    Inventor: Kiyoshi Okuyama
  • Patent number: 11404419
    Abstract: A semiconductor memory cell having an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: August 2, 2022
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Jin-Woo Han
  • Patent number: 11393540
    Abstract: A control circuit on a control die compensates for interference caused by adjacent memory cells on target memory cells on a memory die. The compensation may be based on the data states of the adjacent memory cells. Data latches may be used to store data states of the memory cells. However, reading the target memory cells can over-write the data states of the adjacent memory cells in the data latches. The control die may store data state information for the adjacent memory cells prior to sensing the target memory cells (e.g., prior to a decoding error of a codeword in the target cells). Saving the data state information on the control die reduces storage requirements of the memory die and alleviates the need to sense the adjacent memory cells again if decoding the codeword in the target memory cells fails.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: July 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Bazarsky, Eran Sharon, Idan Alrod
  • Patent number: 11393521
    Abstract: A power module and a memory device are disclosed. The power module includes: a voltage raise unit for outputting a power voltage; an enabling unit connected to the power output for generating and outputting an enabling signal; a control unit, includes: an oscillator, a pulse generator, and an OR operation unit; the oscillator generates a delayed pulse control signal with a certain period; the pulse generator connects to the output terminal of the enabling unit for receiving the enable signal, synchronously generates an instant pulse control signal; the OR operation unit performs OR calculation to the delay pulse control signal and the instant pulse control signal to generate a boost control signal. The output end of the control unit connects to the voltage raise unit, and outputs the boost control signal to the voltage raise unit. The above-mentioned power module has a high transient response capability and maintains the stability of the output power voltage.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: July 19, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Rumin Ji
  • Patent number: 11386935
    Abstract: A charge pump circuit includes a first transistor having a drain connected to an input node, and a source connected to a first node; a second transistor having a drain connected to the first node, and a source connected to an output node; a first capacitor between the first and second nodes; a first inverter including an input node to which a clock signal is supplied and an output node connected to the second node via a first line; a first voltage detection circuit which includes an input node connected to the first line; a third transistor having a source connected to a third node, and a drain connected to the second node; a second inverter including an input node connected to the first voltage detection circuit and an output node connected to a fourth node via a second line; and a second capacitor between the third and fourth nodes.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: July 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Takumi Fujimoto
  • Patent number: 11380396
    Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 5, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventor: Brent Steven Haukness
  • Patent number: 11380695
    Abstract: A memory cell arrangement is provided that may include: one or more memory cells, each of the one or more memory cells including: an electrode pillar having a bottom surface and a top surface; a memory material portion surrounding a lateral surface portion of the electrode pillar; an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure; and a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 5, 2022
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventor: Johannes Ocker
  • Patent number: 11370223
    Abstract: The present subject matter relates to accessing memory units in a memory bank. In an example implementation, a bank select transistor is common to a plurality of memory units in a memory bank. The bank select transistor facilitates accessing a memory unit of the plurality of memory units based on a bank select signal.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: June 28, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Boon Bing Ng, Noorashekin Binte Jamil