Patents Examined by Tan T. Nguyen
  • Patent number: 10777233
    Abstract: A nonvolatile memory device includes a first memory block including a plurality of cell transistors interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines, which are stacked in a direction perpendicular to a substrate, a block selecting circuit that is connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and provides corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines in response to a block selection signal, respectively, and a block unselecting circuit that is connected only with specific string selection lines of the plurality of string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Euihyun Cheon, Byungjun Min
  • Patent number: 10770119
    Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 8, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Su-Chueh Lo, Ken-Hui Chen, Kuen-Long Chang, Ming-Chih Hsieh
  • Patent number: 10768200
    Abstract: An electronic device comprising: a sensor; a communication unit; and at least one processor configured to: receive a first speed measurement from the sensor; receive, via the communication unit, speed information transmitted by an external device; calculate at least one correction parameter based on the first speed measurement and the speed information; and adjust a second speed measurement that is received from the sensor based on the correction parameter.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-Seok Lee
  • Patent number: 10770165
    Abstract: Techniques are described for programming memory cells without performing a verify test, where the programming is followed by a short circuit test. In one aspect, an initial programming is performed on memory cells of a first word line of a block using a program pulse with an initial magnitude, Vpgm. By reading the memory cells, Vpgm can be optimized for programming subsequent word lines. The subsequent word lines may be programmed using a no-verify program operation followed by a word line short circuit test, for one or more word lines involved in the program operation. The short circuit test can be performed concurrently on a single word line, multiple word lines and/or one or more sub-blocks of a block, based on an amount of write data which can be storage by a controller.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 8, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xue Qing Cai, Jiahui Yuan, Deepanshu Dutta
  • Patent number: 10762932
    Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Artur Antonyan
  • Patent number: 10762974
    Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
  • Patent number: 10761980
    Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 10755760
    Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo
  • Patent number: 10748598
    Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ameen D. Akel
  • Patent number: 10748626
    Abstract: A data storage device includes a controller suitable for transmitting a search command; and a nonvolatile memory device suitable for performing an erase page search operation of searching for an erased page among a plurality of pages based on the command, and transmitting information regarding a searched page to the controller.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong
  • Patent number: 10748604
    Abstract: Circuit for triggering the end of a read operation, for a SRAM memory device, comprising: a plurality of pairs of transistors connected to a bit line and an additional bit line, the transistors each having a source connected to a node, the node and the bit lines being, prior to the activation of said given word line, respectively pre-charged via the pre-charging means, then, when said word line is activated, at least the bit lines are disconnected from the pre-charging means, in such a way as to modify the conduction state of certain transistors and consequently cause a variation in the potential of said node until reaching a determined threshold potential that triggers the emission of an end-of-phase signal.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: August 18, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Adam Makosiej, Pablo Royer
  • Patent number: 10741236
    Abstract: A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Akihisa Fujimoto
  • Patent number: 10741566
    Abstract: Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Debra M. Bell
  • Patent number: 10734067
    Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Simon J. Lovett
  • Patent number: 10726926
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLP
    Inventors: Dae Wung Kang, Peter Rabkin, Masaaki Higashitani
  • Patent number: 10724977
    Abstract: Techniques for detecting high impedance conditions in an electrical grid are described herein. In one example, impedance is calculated for each of a plurality of locations within the electrical grid, such as at electrical meters. The impedances may be calculated as a change in voltage divided by a change in current, such as between sequential voltage/current measurements. Statistics may be maintained, including the calculated impedances. In three examples, statistics may be used to identify growth in impedance over multiple days, to identify growth in impedance over multiple hours, and to identify a meter for which impedance is higher than impedance for other meters attached to a single transformer. In a further example, instances of impedance over a threshold value may be identified, from among the maintained statistics. The instances of high impedance may be reported for reasons including cost and safety.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 28, 2020
    Assignee: Itron, Inc.
    Inventors: Robert Sonderegger, Timothy James Driscoll
  • Patent number: 10720202
    Abstract: An apparatus for memory control includes a data storage area configured to store data indicative of a distribution of total current consumption required for a write operation as measured with respect to one or more nonvolatile memory devices of a first type, and a control apparatus configured to evaluate, based on the data indicative of the distribution, a degree to which a total amount of current consumption required for a write operation with respect to a memory area in a nonvolatile memory device of the same first type, regarding a current flowing from a power supply to the nonvolatile memory device during the write operation, is deviated toward larger total current consumptions in the distribution, thereby determining whether the memory area is satisfactory.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Masazumi Maeda, Kazuko Higurashi
  • Patent number: 10714191
    Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
  • Patent number: 10706943
    Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 7, 2020
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Jin-Ki Kim, Peter B. Gillingham
  • Patent number: 10706918
    Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuhsiang Chen, Shao-Yu Chou, Chun-Hao Chang, Min-Shin Wu, Yu-Der Chih