Abstract: An integrated circuit is provided with an independent power framework for a first subsystem and another independent power framework for a processor subsystem that receives messages from the first subsystem.

Abstract: An approach for efficient booting. The approach loads a firmware into a memory from one or more integrated memories, wherein the one or more integrated memories are flash memories on a motherboard. The approach loads an operating system into the memory from the one or more integrated memories. Responsive to loading the operating system into the memory, the approach mounts one or more root filesystems.

Abstract: A level shifter included in a device includes: an external interface power unit configured to supply a power voltage corresponding to electrical input-output characteristics of an interface circuit of an external device; an internal interface power unit configured to supply a power voltage corresponding to electrical input-output characteristics of an internal interface circuit in the device; a power switch unit configured to control power supply to the external interface power unit according to an electrical signal from the external device; and a selector unit configured to control conduction between the interface circuit of the external device and the internal interface circuit, wherein the selector unit is configured to transition to an operable state when the external interface power unit is supplied with power.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.

Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.

Abstract: An approach is described herein that includes a method for power management of a device. In one example, the method includes sampling duration characteristics for a plurality of past idle events for a predetermined interval of time and determining whether to transition a device to a powered-down state based on the sampled duration characteristics. In another example, the method includes determining whether an average idle time for a plurality of past idle events exceeds an energy break-even point threshold. If the average idle time for the plurality of past idle events exceeds the energy break-even point threshold, a device is immediately transitioned to a powered-down state upon receipt of a next idle event. If the average idle time for the plurality of past idle events does not exceed the energy break-even point threshold, transition of the device to the powered-down state is delayed.

Abstract: An improved method and apparatus for performing power management in a memory device is disclosed.

Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

Abstract: Methods and apparatus for enhanced control over electronic device manufacturing systems are provided herein. In some embodiments, the integrated sub-fab system may employ Ethernet and/or RS232 Serial communications through an open platform of apparatus to achieve a reduced carbon footprint during electronic device manufacturing. For this example, the system could include a process tool set and controller linked by sensors or software interconnect with one or more sub-fab or local factory auxiliary systems that can be operated in one or more states of energy consumption. These one or more auxiliary systems can be switched between different levels of energy consumption, as required by the process, via the controller. For many auxiliary components or systems the integrated sub-fab system utilizes existing signal outputs, for others they may employ secondary sensors or monitors.

Abstract: A rack-style computer system is provided. The computer system includes a first server, a second server, and a power distribution unit (PDU). The PDU supplies power to the first server and the second server and monitors the power supplied to the first server and the second server and obtains a power sum value. The first server determines whether the power sum value exceeds a predetermined threshold, and if the determination is affirmative, the first server performs a power throttling.

Abstract: A rack-style computer system is provided. The computer system includes a first server, a second server, and a power distribution unit (PDU). The PDU supplies power to the first server and the second server and monitors the power supplied to the first server and the second server and obtains a power sum value. The first server determines whether the power sum value exceeds a predetermined threshold, and if the determination is affirmative, the first server performs a power throttling.

Abstract: An information processing apparatus includes a monitoring unit that monitors a reception of a power-on instruction from a second control device among the plurality of control devices, and a prevention unit that prevents an issue of the power-on instruction to the second control device when the monitoring unit detects the power-on instruction from the second control device. Therefore, the control device can prevent the occurrence of unintended power-on operations.

Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.

Abstract: A system and method of coordinating power states between two detachable units is disclosed. Only the primary unit has a user-controllable power control. The secondary unit is not directly user controllable. The power states of the two units are coordinated using an actuator mechanism when the units are attached. When the two units are detached, the state of the secondary unit is dependent upon the state of the primary unit and any subsequent commands transmitted by the primary unit to the secondary unit.

Abstract: An integrated circuit system comprising a first chip including a first period signal generation unit configured to generate a first period signal, transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip, and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate codes corresponding to a difference between periods of the first period signal and the second period signal, and a delay unit configured to delay the second signal by using a delay value that is changed according to the codes.

Abstract: Method of cooperative reduced power mode suspension for high input/output (‘I/O’) workloads, including: determining, by a transfer monitoring module, a size of a file to be transferred to a recipient, wherein the recipient includes a central processing unit (‘CPU’) operating in a reduced power mode; determining, by the transfer monitoring module, a desired transfer rate for transferring the file to the recipient; calculating, by the transfer monitoring module, an expected transfer completion time in dependence upon the size of the file and the desired transfer rate; and sending, by the transfer monitoring module, a message to the recipient requesting that the CPU suspend the reduced power mode in dependence upon the expected transfer completion time.

Abstract: A method for managing the power of a chassis includes receiving a plurality of modular information handling systems into the chassis, receiving a plurality of information handling resources into the chassis, virtualizing access of one of the modular information handling resources to two or more of the plurality of modular information handling systems, the modular information handling systems sharing the modular information handling resource, and, upon initialization of one of the information handling systems, determining power requirements of the shared information handling resource, receiving power requirements from the information handling systems, determining whether the power requirements from the information handling system includes power requirements of the shared information handling resource, subtracting the power requirements of the shared information handling resource from the power requirements of the information handling system to determine resultant power requirements, comparing the resultant pow