Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: In response to an instruction by a user, or by performing reception, detection and assumption processing, the presence state of the user is determined, and corresponding presence mode conversion data are acquired and are set as user presence data. When the presence mode conversion data are referred to, and processing that corresponds to the user's presence state is performed: when the user is present, urgent mail is transmitted, and when the user is absent, a message for the user is accepted.

Abstract: An integrated circuit having statistical processing capability. The integrated circuit has an input for receiving input data in a first data domain. A data converter is provided for converting received input data from the first domain to a second domain different from the first domain. A statistical processor is provided for obtaining statistical information from the output of the data converter and processing the obtained statistical information in accordance with a predetermined processing algorithm. An output on the integrated circuit allow access of the processed statistical information by the statistical processor external to the integrated circuit.

Abstract: In a computer (e.g. an 80×86-compatible personal computer) in which peripheral devices (e.g. hard drives, floppy drives, CD-ROMs, etc.) are accessed through more than one chain of handlers for the peripheral devices (e.g. via interrupts 13h and 40h), an improved device handler for a peripheral device (e.g. a device that complies with the “El Torito” standard) is inserted in both chains (e.g. by “hooking” both interrupts 13h and 40h), so the device handler cannot be bypassed when an access request directed to the device handler is passed through either chain and so the device handler can direct the access request to the next device handler in the correct chain, when appropriate.

Abstract: A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory region. Requests for memory are mapped at least once, for example from virtual to physical page numbers. The I/O requests are conditionally remapped to pages in the first region as a function of how often they are involved in the I/O operations and would normally otherwise need to be copied. Remapping may also be made conditional on a function of availability of memory in the first region. In a preferred embodiment of the invention, the I/O requests are initiated by a subsystem within a virtual machine, which runs via an intermediate software layer such as a virtual machine monitor on an underlying hardware and software platform. A typical application of the invention is DMA.

Abstract: A CPU unit writes a command for instructing a control CPU specified information for each I/O unit, each I/O unit decodes a command instructed by the CPU unit so as to determine whether or not it is information specified by the control CPU, and holds the corresponding information specified by the control CPU in the I/O unit, the CPU units issue commands for instructing the reset control to all the I/O units, and each I/O unit decodes the command instructing its reset control, and when it has determined that the corresponding command is instructed from the CPU unit of the controlling end, it follows the reset controlling instruction so that the resetting operation of the specific I/O unit on the system specified by the CPU unit is controlled.

Abstract: Context or other functional settings are protected during a power up reset sequence in a computer system, without the need to save such context or settings in static memory. A signal, representing a change in the context, is delayed beyond a critical period of indeterminacy resulting from a power up sequence. Reliable signals, set before an application of power, negotiate the delay prior to an assertion of a power up reset signal. The context or settings are preserved by bypassing the reset signal. Unreliable signals, set during an application of power, are held by the delay to allow the reset signal to clear or initialize the context or settings. The reset function operates without prior knowledge, for example as saved in static memory, of the state of the context.

Abstract: A method and system for using a new bus identifier in an interconnect, and the interconnect including a plurality of nodes and at least one bus bridge. A configuration change is determined on the first bus connected to the plurality of nodes. Each node has a corresponding bus identifier. A new bus identifier is assigned for each node having a changed state if a configuration change is determined on the first bus.

Abstract: A recording/reproducing apparatus using an IC memory includes an IC memory to/from which writing/reading of an audio signal is performed; and a control circuit for controlling writing/reading of the audio signal to/from this IC memory, and its address, and for controlling, on writing and reading the audio signal to and from the IC memory, so that its address becomes ring-shaped, writing, of when a recording key is pressed, the audio signal from contiguous address to an area, within the IC memory where the writing, which has never been read is performed, and reading, of when a reproduction key is pressed, the audio signal from the head of an area within the IC memory where the writing, which has never been read, is performed.

Abstract: It is provided a data storage device which reads data from and/or writes data to a memory medium, comprising: a storage unit for storing a first identifier; an identifier acquisition unit for acquiring a second identifier recorded on a memory medium which is set to said data storage device; and a controller for comparing said first identifier with said second identifier, and controlling to access to said memory medium for data reading and/or writing according to a relationship between said first identifier and said second identifier. For example, when the first identifier does not match the second identifier, the controller inhibits access to the memory medium for the reading and writing of data. But when the first and the second identifiers match, the controller permits access to the memory medium for the reading and writing of data.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A point-of-sale system is disclosed which is freely configurable with a plurality of peripheral input devices. The system includes a general purpose computer having a communications port for receiving and/or transmitting data. An electronic interface is coupled to the communications port and readily connectable to the plurality of peripheral input devices for communicating data between the plurality of input devices and the computer. The plurality of peripheral input devices can be selectively connected and disconnected from the electronic interface, the electronic interface maintaining a continuous dialogue with the computer during the connection and disconnection of the input devices.

Abstract: In a heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems, an I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least one disk connected to the I/O subsystem B in a magnetic tape library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A system for programming a periphery flash ROM is provided. The system in-cludes a host computer, an IDE interface, a flash controller, a flash ROM, and a micro-processor. The flash controller is coupled to the host computer through the IDE interface. The flash ROM and the microprocessor are also coupled to the flash controller. When the system enters a flash ROM programming mode, task files used between the IDE interface and the host computer are redefined by the host computer and is interpreted by the flash controller so that a firmware code from the host computer is written into the flash ROM through the flash controller. After the flash ROM is completely programmed, the task files return to their original definition. The microprocessor is required to disable the access to the flash ROM during the flash ROM programming mode.

Abstract: A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.

Abstract: A method and apparatus for allowing several applications to share a single video overlay resource via multiplexing are disclosed. The multiplexing is accomplished from the application end through a multiplexing abstraction layer provided to the developers of end applications as an application program interface. Through the application program interface, each application may, at any time, request, release, or modify the attributes of the video overlay device such as picture quality, tuning, source, etc. The application program interface provides all basic functionality of the hardware as accessible through other means including normal operating system support and device driver services.

Abstract: A method and apparatus for interfacing a weighing scale and one or more peripheral devices which includes a single intelligent interface cable assembly connected between a weighing scale and a plurality of peripheral devices, the IICA detects the peripheral device protocol by receiving a logic signal indicating which protocol is in operation, if necessary, the IICA then switches the signal protocol of the weighing scale to correspond with the signal protocol of the detected peripheral device protocol. Simultaneous, tripping of a mailing machine to print postage amounts may occur.

Abstract: A system for handling write requests is described. The system uses two queues for storing posted write requests. When a posted write error results, software handles the posted write error using information stored in a first queue of the two queues. The write request producing the posted write error is cleared from the second queue which continues to handle physical packets containing write requests.

Abstract: An automatic addressing technique for flexibility specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.