Patents Examined by Taniae M. Thomas
  • Patent number: 5843812
    Abstract: An improved p+ polysilicon gated PMOSFET having a channel on the surface of a silicon substrate and improved short channel behavior is disclosed. A simplified process allows making a p+ doped gate and source/drain regions at the same time, the transistor particularly having a stable threshold voltage. The disclosed method provides the steps of: (A) forming an active region and an insulation region on an n-type semiconductor substrate; growing a gate insulating layer on the silicon substrate; depositing a polysilicon layer on the gate insulating layer; annealing the polysilicon layer in the presence of NH.sub.3 or other nitrogen-containing gas; (C) forming a gate line by patterning and etching the polysilicon layer; and (D) implanting BF.sub.2 ions into the semiconductor substrate.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: December 1, 1998
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Hyunsang Hwang