Abstract: Disclosed are a light emitting device which has improved reliability by increasing bonding force between a cathode and organic layers contacting both surfaces thereof, and a transparent display device using the same.

Abstract: An display panel and a display device are provided, the display panel having a display region defined therein, the display region including: a regular display region; and an irregular display region located at corners of the regular display region, the irregular display region comprising a first region and a second region which is located at edges of the irregular display region and outside the first region; the first region is provided with a plurality of first pixels therein, and the second region is provided with a plurality of second pixels therein, each of the plurality of second pixels having an area smaller than that of each of the plurality of first pixels.

Abstract: An electro-luminescent display device includes an anode disposed on a substrate; a bank having an opening that exposes a portion of the anode and having an undercut structure adjacent to the opening; a dummy pattern disposed at the undercut structure of the bank; an organic light-emission layer disposed on the anode and electrically disconnected with at least one of adjacent pixels; and a cathode disposed on the organic light-emission layer.

Abstract: An organic light emitting display device includes a first pixel; and a second pixel being adjacent to the first pixel, wherein each of the first pixel and the second pixel includes a plurality of subpixels, and wherein the first pixel and the second pixel share at least one subpixel of the plurality of subpixels.

Abstract: Provided are an array substrate, a display panel and a display device. The array substrate includes a display region and a peripheral region. The peripheral region includes a chip-on-film bonding region, and the peripheral region has a recessed structure configured to fill a bonding material. The recessed structure is between the chip-on-film bonding region and a lateral side of the array substrate. The chip-on-film bonding region is between the display region and the lateral side. By disposing a recessed structure configured to fill the bonding material in the peripheral region, a gap is difficult to occur between the chip-on-film in the chip-on-film bonding region and the array substrate, preventing entry of water vapor to cause corrosion of lead wires and short circuits of lead wires. The defect ratio of the array substrate, the display panel, and the display device is reduced, and the product quality is improved.

Abstract: This disclosure relates to an array substrate and a display device. The array substrate includes a display area and a lead area, the display area including a plurality of signal lines, and the lead area including fanout lines connected with the signal lines, wherein the lead area further includes capacitance adjustment sections non-electrically connected with at least one of the fanout lines, the capacitance adjustment sections are at a layer different from a layer where at least one of the fanout lines is.

Abstract: An imaging device including a semiconductor substrate; pixels arranged on the semiconductor substrate in a first direction; and a signal line extending in the first direction. Each of the pixels includes a photoelectric converter generating signal charge by photoelectric conversion, a charge accumulation region that accumulates the signal charge output from the photoelectric converter, a first transistor that outputs a signal to the signal line according to an amount of the signal charge accumulated in the charge accumulation region, a capacity circuit that is coupled to a gate of the first transistor and that includes a first capacitive element, the first capacitive element including a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, at least one of the first electrode and the second electrode containing a metal. The first capacitive element is closer to the semiconductor substrate than the signal line.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: The present disclosure is directed to an organic light emitting diode display device includes a substrate having an emitting area and a non-emitting area; an overcoating layer on a first surface of the substrate and including a plurality of convex portions and a plurality of concave portions, at least one of the plurality of convex portions including a bottom surface portion, a top surface portion and a side surface portion between the bottom and top surface portions; a light emitting diode on the overcoating layer; and a cholesteric liquid crystal layer at a transmission direction of a light emitted from the light emitting diode.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: A light-emitting display device is provided. The light-emitting display device includes a first substrate, a first electrode layer on the first substrate, a bank layer that has openings exposing part of the first electrode layer, an emissive layer on the first electrode layer, bank grooves formed by recessing the bank layer, a second electrode layer on the emissive layer, and a low-reflectivity layer that lies on the second electrode layer and is positioned to correspond to the bank grooves.

Abstract: A method for manufacturing a semiconductor device includes doping a substrate with a dopant to form a first well region of a first circuit and a second well region of a second circuit; forming a semiconductor fin extending over the first and second well regions, wherein a first section of the semiconductor fin on the first well region has a width different from a second section of the semiconductor fin on the second well region; forming a first gate electrode across first section of the first semiconductor fin and a second gate electrode across the second section of the semiconductor fin; and forming a first source/drain region adjoining the first section of the semiconductor fin and a second source/drain region adjoining the second section of the semiconductor fin.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

Abstract: A display substrate and a method of preparing the same, and a display device are provided, the method including: providing a substrate; forming a switching thin film transistor precursor and a driving thin film transistor precursor on the substrate, each including a semiconductor layer, a gate insulating material layer and a gate metallic layer stacked sequentially above the substrate; forming a photoresist layer above the switching thin film transistor precursor and the driving thin film transistor precursor, and forming an etching mask from the photoresist layer, a first portion of the etching mask at the switching thin film transistor precursor and a second portion of the etching mask at the driving thin film transistor precursor having different shapes; and forming a switching thin film transistor and a driving thin film transistor, by etching processing the switching thin film transistor precursor and the driving thin film transistor precursor with the etching mask.

Abstract: Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.

Abstract: A display device may include a display configured to emit light for displaying an image, a microlens array on the display and configured to collimate the image incident from the display so as to be delivered to the eyes of a user, the microlens array including a refractive index conversion layer in which a refractive index varies from region to region, and an optical path adjustment layer configured to collect light, emitted from the display and transmitted by the microlens array, and to space the display and the microlens array a preset distance apart from each other. Here, the refractive index conversion layer may include a polymer and liquid crystal molecules that interact with the polymer.

Abstract: The invention allows stable fabrication of a TFT circuit board used in a display device and having thereon an oxide semiconductor TFT. A TFT circuit board includes a TFT that includes an oxide semiconductor. The TFT has a gate insulating film formed on part of the oxide semiconductor and a gate electrode formed on the gate insulating film. A portion of the oxide semiconductor that is covered with the gate electrode 104 and a portion of the oxide semiconductor that is not covered with the gate electrode are both covered with a first interlayer insulating film. The first interlayer insulating film is covered with a first film 106, and the first film is covered with a first AlO film.

Abstract: An organic light emitting diode array substrate and an electronic device. The organic light emitting diode array substrate includes a display region, and a first package test electrode and a first package test lead which are outside the display region. The display region includes a first power supply line and a first signal line; the first package test lead is configured to connect the first package test electrode with the first power supply line to provide a first supply voltage for the display region; the first signal line is configured to provide a first electrical signal for the display region; and a thermal conductivity of the first package test lead is higher than a thermal conductivity of the first signal line.