Abstract: A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency divider to produce a second clock signal having a second frequency, measuring the second clock signal with a digital control circuit, and programming a programmable digital frequency divider with the digital control circuit, such that the second clock signal corresponds to the presettable clock signal.
Abstract: A transmitter transmits a spread spectrum pilot and data signal. Each signal has an associated chip code. A receiver receives the transmitted pilot and data signal. The received pilot signal is filtered using the pilot chip code and weights are determined for components of the received pilot signal using an adaptive algorithm. The received data signal is weighted by the determined weights and filtered with the data signal chip code to recover data from the received data signal.
Type:
Grant
Filed:
September 11, 2000
Date of Patent:
August 21, 2001
Assignee:
InterDigital Technology Corporation
Inventors:
David K. Mesecher, Alexander Reznik, Donald Grieco, Gary Cheung