Patents Examined by Terrence M Mackey
  • Patent number: 6686292
    Abstract: A method for forming a patterned composite stack layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing dielectric layer. There is then formed upon the blanket silicon containing dielectric layer a patterned photoresist layer.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: February 3, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Szu-Hung Yang, Sheng-Liang Pan
  • Patent number: 6653239
    Abstract: This invention relates to the construction of microfabricated devices and, in particular, to types of microfabricated devices requiring thermal isolation from the substrates upon which they are built. This invention discloses vertical thermal isolators and methods of fabricating the vertical thermal isolators. Vertical thermal isolators offer an advantage over thermal isolators of the prior art, which were substantially horizontal in nature, in that less wafer real estate is required for the use of the vertical thermal isolators, thereby allowing a greater density per unit area of the microfabricated devices.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: November 25, 2003
    Assignee: Xactix, Inc.
    Inventor: Kyle Lebouitz
  • Patent number: 6641743
    Abstract: A method for forming waveguides in an optical material such as lithium niobate comprises the steps of providing an exchange agent including a proton-supplying medium and a catalyst, and exposing a selected portion of the optical material to the exchange agent for a predetermined time and at a predetermined temperature. Preferably, the catalyst is a metallic cation having a valence of at least +2, and the proton-supplying medium is a weak acid with a pKa of greater than about 4.5 or a lithium-buffered (“starved”) acidic solution. The catalyst accelerates the rate at which protons are exchanged with corresponding ions in the optical material lattice, thereby reducing the time required to produce a waveguide in the exposed portion of the optical material.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: November 4, 2003
    Inventors: Mark L. F. Phillips, Travis P. S. Thoms
  • Patent number: 6596187
    Abstract: A method of forming a nano-supported sponge catalyst (10) on a substrate (12) is comprised of depositing an active catalytic metallic element (16) on the substrate (12) and depositing a structural metallic element (18) with the active catalytic metallic element (16) to form a mixed metal alloy layer (14). The method is further comprised of etching the mixed metal alloy layer (14) with an etchant to oxidize the active catalytic metallic element (16) and the structural metallic element (18) and to remove at least a portion of the structural metallic element (18) from a first sub-layer of the mixed metal alloy layer (14). The first sub-layer of the mixed metal alloy layer (14) is porous and comprised of nano-particles of the active catalytic metallic element (16) that are supported by a metal oxide structure derived from the structural metallic element (18).
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: July 22, 2003
    Assignee: Motorola, Inc.
    Inventors: Bernard F. Coll, Yi Wei
  • Patent number: 6583066
    Abstract: A method for etching an oxide-nitride-oxide (ONO) layer fabricated on a semiconductor wafer, the ONO layer including a lower oxide layer, a nitride layer located over the lower oxide layer, and an upper oxide layer located over the nitride layer. The method includes the steps of removing the upper oxide layer and a portion of the nitride layer using an isotropic plasma enhanced etch, and then removing the remainder of the nitride layer and a portion of the lower oxide layer using an isotropic plasma enhanced etch, wherein the semiconductor wafer is not exposed through the lower oxide layer. The method can be used to form gate electrodes and diffusion bit liens in a fieldless array of non-volatile memory cells.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: June 24, 2003
    Assignee: Tower Semiconductor, Ltd.
    Inventors: Efraim Aloni, Shai Kfir, Menchem Vofsy, Avi Ben-Guioui
  • Patent number: 6572782
    Abstract: Recycling process for CdTe/CdS thin film-solar cell modules in which the modules are mechanically disintegrated into module fragments, the module fragments are exposed to an oxygen-containing atmosphere at a temperature of at least 300° C. causing a pyrolysis of adhesive material contained in the module fragments in form of a hydrocarbon based plastics material and the gaseous decomposition products that are generated during the pyrolysis are discharged, and, afterwards, the module fragments freed from the adhesive means are exposed to a chlorine-containing gas atmosphere at a temperature of more than 400° C. causing an etching process wherein the CdCl2 and TeCl4 that are generated in the etching process are made to condense and precipitate by cooling.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: June 3, 2003
    Assignee: ANTEC Solar GmbH
    Inventors: Manuel Diequez Campo, Dieter Bonnet, Rainer Gegenwart, Jutta Beier