Patents Examined by Terri Lynn Smith
  • Patent number: 6973717
    Abstract: A semiconductor device in chip format having a chip which has at least one first insulating layer and electrical connection pads free of the insulating layer is described. On the first insulating layer, interconnects run from the electrical connection pads to base regions of external connection elements. A further applied insulating layer is provided with openings leading from the outside to the base regions of the external connection elements. In the openings there is a conductive adhesive, onto which small balls which are metallic at least on the outside are placed. The semiconductor element can also contain a solder paste instead of a conductive adhesive in the openings, and metallized small plastic balls are placed onto the solder paste. The invention furthermore relates to methods for producing the semiconductor device described.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: December 13, 2005
    Assignee: Infineon Technologies AG
    Inventors: Hans-Jürgen Hacke, Klaus-Peter Galuschki
  • Patent number: 6971166
    Abstract: A method of manufacturing a non-reciprocal component including a casing having an input/output terminal and a ground terminal formed therein, a ferrite plate, a line conductor, and a magnet disposed in the casing, and an upper yoke and a lower yoke provided at the top face and the bottom face of the casing, respectively. In the non-reciprocal component, the casing is insert-molded with the lower yoke so that a portion of the casing penetrates through the lower yoke. A side of the component is defined partly by the lower yoke and partly by the penetrating portion of the casing. An input/output terminal and a ground terminal in the casing are defined by respective portions of a molded hoop material.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: December 6, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshihiro Makino, Hiroki Dejima, Takashi Kawanami, Takashi Hasegawa, Masakatsu Mori, Takahiro Jodo
  • Patent number: 6968613
    Abstract: A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed from the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: November 29, 2005
    Assignee: UltraTera Corporation
    Inventors: Chung-Che Tsai, Jin-Chuan Bai
  • Patent number: 6964095
    Abstract: A method of manufacturing an electrical contact with a crimp ear from a flat ribbon of conductive material including applying a force to the ribbon to form an adjacent pair of approximately semicylindrical depressions on opposite sides of the centerline of the ear, shearing the ribbon at the depression bisectors to form a pair of legs on opposites of the centerline, and forming the legs into a predetermined shape about the centerline. Forming the legs includes straightening the legs and bending the legs to the appropriate predetermine relative angle. Optionally, the ear is coined. Optionally, serrations are inscribed across the ear.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: November 15, 2005
    Assignee: Etco, Inc.
    Inventor: Ralph Jacques
  • Patent number: 6964093
    Abstract: An electronics packaging system (1) including a printer (3), a placing unit (4) and a reflow unit (5), wherein a printed wiring board (2) is carried while being kept in an upright position. The printed wiring board (2) has solder printed on all the lands thereof at the same time, the electronic parts (10) are all placed on the lands at the same time, and the electronic parts (10) are all soldered to the lands at the same time. Thus, the system (1) can be designed more compact, and the electronic parts packaged in a shorter time.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: November 15, 2005
    Assignee: Sony Corporation
    Inventors: Kazuhisa Mochida, Katsumi Togasaki, Katsumi Morita, Yusuke Masutani, Hiroji Kameda, Noboru Sekiguchi, Minoru Shimada, Toshio Toyama, Akihiro Koga, Mitsuo Inoue, Kazuhiro Abe, Tetsuya Yonemoto, Kenji Ishihara, Syunji Aoki, Fumio Matsumoto, Takanori Arai, Hisashi Naoshima