Patents Examined by Terry Cunnigham
  • Precise delay line circuit with predetermined reset time limit
    Patent number: 5801568
    Abstract: A delay line circuit is provided that precisely delays the incoming referenced clock signal by utilizing two delay cells and a sample-and-hold circuit. The circuit eliminates the need for sensing circuitry at the output to determine if the need to monitor the delay line circuit is operating in an undesirable operation. By eliminating the sensing circuitry the reliability of delay line circuit is significantly increased.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: September 1, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David Young