Abstract: The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal.

Abstract: A frame guard system comprises forward and backward guard circuits respectively having different guard stage numbers. A time after output of a frame alignment signal until first arrival of a pseudo out-of-frame signal is measured and the guard stage number of the forward guard circuit is switched in accordance with the measured time; whereas, a time after stoppage of the output of the frame alignment signal until first arrival of a pseudo synchronization signal is measured and the guard stage number of the backward guard circuit is switched in accordance with the measured time. In this way, since the respective guard stage numbers of the forward and backward guard circuits can be changed depending on a situation, the out-of-frame state after the determination of the synchronization can be prevented and thus a stable communication can be realized at all times.

Abstract: The presence of a communication signal having a predetermined recognition pattern of symbols that occur at a predetermined rate (1/T) is detected by processing the communication signal to extract in-phase (I) and quadrature-phase (Q) components of the symbols; processing the extracted components to compute a complex autocorrelation function of the extracted components with a time parameter equal to an integer multiple (nT) of the symbol period (T); integrating the complex autocorrelation function over a substantial portion of the recognition pattern; and comparing the magnitude of the integrated complex autocorrelation function with a predetermined threshold value to detect the presence of the recognition pattern.

Abstract: In a coherent M-ary PSK demodulator, an M-ary PSK detector demodulates a received M-ary PSK modulated convolutional code with a carrier recovered by a voltage-controlled oscillator to produce first and second channels of demodulated convolutional codes. A convolutional decoder decodes the signals of the first and second channels while correcting bit errors. An error rate detector is provided for detecting when the number of such errors occurring during a specified period of time is smaller than a predetermined value and generates a signal indicating that the convolutional decoder is synchronized with the demodulated signals. The power levels of signal and noise components of the demodulated channels are detected by a power detector.