Abstract: For synchronising the data transmission between a CMOS circuit (1) and a bipolar circuit (2) a DLL (delayed lock loop) is provided which sets a phase deviation between the operating clocks (CLK1, CLK2) of the two circuits (1, 2), and changes the phase of at least one of the two clocks (CLK1, CLK2) according to this phase deviation, until the two clocks are in phase, in such a way that the data (DATA1) provided by the first circuit (1) can then be taken on by the second circuit (2). To this end, the DLL circuit comprises a phase detector (6), a loop filter (7) and an adjustable element (8).

Abstract: A method, device, and system in which radio links between relays and users are optimized separately from the links between relays and base stations and in which multiple simultaneous data streams between relays and base stations are created. The system includes transceivers of at least three kinds with two kinds of radio interfaces. The first kind of transceiver, a base station (BS), is connected to the core network with a link of wire line quality. The second kind, a relay station (RS), is connected to the BS with a first radio interface, and to the third kind, the user equipment (UE), with a second radio interface. The first and second radio interfaces can operate, at least in part, using the same frequency bandwidth. The UE can also connect directly to the BS using the second radio interface if the BS is closer than any RS.

Abstract: A predistortion power amplifier architecture has a power amplifier which receives an input via an amplitude modulator and a phase modulator. A sample of the output of the amplifier and a sample of the input to the amplifier are applied to an adaptive pre-distorter subsystem. The adaptive pre-distorter generates a gain correction signal which is applied to the amplitude modulator and a phase correction signal which is applied to the phase modulator. This serves to predistort the input signal to the power amplifier to compensate for non-linearities in the power amplifier. A switching arrangement alternately couples a sample of the input and output of the amplifier to a first and a second envelope detector. The outputs of the envelope detectors are applied to a difference amplifier. The switching arrangement has a chopping action on the signals which helps to offset imbalances in the characteristics of the two envelope detectors.

Abstract: Decreasing the average transmitted power in an optical fiber communication channel using multilevel amplitude modulation in conjunction with Pulse Position Modulation (PPM). This multilevel PPM method does not entail any tradeoff between decreased power per channel and channel bandwidth, enabling a lower average transmitted power compared to On/Off Keying (OOK) with no reduction in aggregate data rate. Therefore, multilevel PPM can be used in high-speed Dense Wavelength Division Multiplexed (DWDM) systems where the maximum number of channels is traditionally limited by nonlinear effects such as self-phase modulation (SPM), cross-phase modulation (XPM), four-wave mixing (FWM), stimulated Brillouin scattering (SBS), and stimulated Raman scattering (SRS). This modulation technique can enable an increased number of channels in DWDM systems, thereby increasing aggregate data rates within those systems.

Abstract: A PLL circuit (1) is regulated by means of a digital modulation signal (28) at a first frequency, and is then regulated at a second frequency, by deactivation of the digital modulation signal (28). A difference signal (32), which is characteristic of the voltage change in a control signal (22) for the VCO (7) which is produced by deactivation of the digital modulation signal (28) is compared with an analog modulation signal (34). The analog modulation signal (34) is changed so as to correct any discrepancy determined during the comparison.

Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods for wireless combined-signal communication. For example, a method in accordance with an embodiment of the invention may include transmitting a combined signal over a combined channel by mapping a first block of said combined signal to be carried by a first sub-channel of said combined channel and mapping a second block, substantially identical to said first block, to be carried by a second sub-channel of said combined channel.

Abstract: Systems and methods for transmitting information at very high data rates through narrowband communication channels are provided. The systems and methods involve modulating a message signal with a novel return-to-zero, abrupt phase modulation technique and filtering the modulated signal with a sophisticated high-precision digital filter. The digital filter is designed based on fractal modeling of the frequency spectrum of the modulated signal. The systems and methods of the present invention enable data rates exceeding 5 Mbps to be delivered through frequency channels as narrow as 50 KHz under a variety of channel conditions.

Abstract: A decision feedback equalizer (DFE) for a receiver that can reduce jitter is disclosed. The DFE uses an equalizer structure that employs a symbol sampling operation at a decision device, also known as a slicer. In a receiver, the phase of a signal, such as an equalized signal, is typically estimated from zero crossings in the clock recovery operation. Fluctuations in these zero crossings makes phase of the reproduced clock unstable, which decreases error performance in an associated receiver. Embodiments advantageously align inter-symbol interference (ISI) canceling terms from a feedback filter (FBF) relatively well, and thereby provide equalization of a relatively large portion of a symbol period. This advantageously stabilizes the phase of an equalized signal and reduces jitter.