Abstract: In a computer system, when a first high availability (HA) pair is configured with a first logical device of a first storage apparatus and a second logical device of a second storage apparatus, the first logical device is virtualized on a third storage apparatus and is set to correspond with a third logical device of the third storage apparatus. A fourth storage apparatus virtualizes the second logical device and sets the second logical device to correspond with a fourth logical device of the fourth storage apparatus. After a second HA pair is configured with the third logical device and the fourth logical device, the data on the first logical device is migrated to the third storage apparatus and managed as data on the third logical device. The data on the second logical device is migrated to the fourth storage apparatus and managed as data on the fourth logical device.

Abstract: Systems and methods for determining an access pattern in a computing system. Accesses to a file may contain random accesses and sequential accesses. The file may be divided into multiple regions and the accesses to each region are tracked. The access pattern for each region can then be determined independently of the access patterns of other regions of the file.

Abstract: The embodiments relate to a computer system, computer program product and method for managing a garbage collection process. Processing control is obtained based on execution of a load instruction and a determination that an object pointer to be loaded indicates a location within a selected portion of memory undergoing a garbage collection process. The determination includes identifying a base address and size of a first memory block subject to the garbage collection, and assigning a binary value to each first memory block section. An image of the load instruction is obtained and a pointer address is calculated from the image. It is determined whether the object pointer is to be modified. The object pointer is modified and stored in a selected location.

Abstract: A nonvolatile memory device includes a nonvolatile memory cell array, where N bits are stored in a single memory cell (N being an integer greater than or equal to 2), and a page buffer circuit electrically connected to the nonvolatile memory cell array. The page buffer circuit includes at least N latches configured to temporarily store data. A data input/output circuit connected to the page buffer circuit receives programmed input data and provides the input data to the page buffer circuit. A control logic controls the page buffer and initializes a target latch value before receiving all input data of a program unit from the data input/output circuit.

Abstract: A storage apparatus includes a backup controller and a remote copy controller. The backup controller identifies a common data area being an area storing data common to a first volume and a second volume, each of the volumes including a storage area capable of storing data. The backup controller transmits an instruction to a backup destination storage apparatus including a backup volume, the instruction causing to copy, in the backup destination storage apparatus, data stored in the common data area, from a backup volume of the second volume to a backup volume of the first volume. The remote copy controller transmits at least part of data stored in an area different from the common data area in the first volume to the backup destination storage apparatus.

Abstract: A storage device may include one or more nonvolatile memory devices and a controller. The nonvolatile memory devices may be configured to store target data. When the number of operations which is performed on the target data is equal to or greater than a first reference value, the controller may be configured to store duplicated data, which is identical to some or all portions of the target data, in the nonvolatile memory devices. When the number of operations performed on the target data becomes equal to or smaller than a second reference value after the duplicated data is generated, the controller may be configured to invalidate the duplicated data.

Abstract: A pinned memory space for caching data can be provided in a data node. The data that is cached in the pinned memory space can be prevented from being swapped out. A virtual address can be assigned to the data. The virtual address can be mapped to a memory address of the data in the pinned memory space for accessing the data by an application. A first command can be received from the application for caching the data. The first command can indicate an attribute associated with the caching of the data. Responsive to receiving the first command from the application for caching the data, the data associated with the first command can be cached by storing the attribute in association with the data in the pinned memory space.

Abstract: In response to determining, by a storage controller, that a first process is to perform a write operation, a customer data track in a cache is configured for exclusive access while waiting for the write operation on the customer data track to be performed by the first process. In response to configuring the customer data track for the exclusive access, a copy of a metadata track is generated, wherein the metadata track stores metadata information of the customer data track and is configured for shared access. The copy of the metadata track is configured to provide exclusive access to a second process to perform operations on the copy of the metadata track, wherein the first process is able to perform the write operation on the customer data track that causes the metadata track to be updated while the second process performs the operations on the copy of the metadata track.

Abstract: A memory system includes: a memory device including a plurality of memory blocks; and a controller including a memory, the controller being suitable for: selecting a source memory block and a target memory block among the plurality of memory blocks; loading map segments of map data for the source memory block on the memory; determining valid pages, among a plurality of pages included in the source memory block, through the map segments; loading valid data stored in the valid pages on the memory; updating map data for the valid data; and storing the valid data and the updated map data in a plurality of pages included in the target memory block.

Abstract: A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.

Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.

Abstract: A method for processing a memory page in memory, where the memory page in the memory includes an idle single-level cell (SLC) memory page, an active SLC memory page, an inactive SLC memory page, and a multi-level cell (MLC) memory page, and when a quantity of idle SLC memory pages of any virtual machine (VM) is less than a specified threshold, the processing method includes converting one idle SLC memory page to two MLC memory pages, copying data in two inactive SLC memory pages to the two converted MLC memory pages, and releasing storage space of the two inactive SLC memory pages to obtain two idle SLC memory pages.

Abstract: A power management system for stack memory thread tasks according to some examples of the disclosure may include a non-collapsible memory region, a collapsible memory region configured below the non-collapsible memory region, a memory management unit in communication with the non-collapsible memory region and the collapsible memory region, the memory management unit operable to allocate a portion of the non-collapsible memory region and a portion of the collapsible memory region to a thread task upon initialization of the thread task and power down the portion of the collapsible memory region allocated to the thread task upon receiving a power down command.

Abstract: A data storage device includes a host interface unit for generating a host request based on a request received from a host device; a control unit for generating a task based on the host request; and a memory control unit for controlling a nonvolatile memory device based on the task, wherein, when it is determined that an operation of the nonvolatile memory device has failed, the memory control unit transmits a fail information regarding the failed operation to the host interface unit.

Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.

Abstract: Managing data stored in a Data Storage Device (DSD) including a memory. A translation table is maintained mapping logical addresses for data to physical addresses corresponding to a location where the data is stored in the memory. A data pattern is identified of particular data to be stored in the memory or of particular data already stored in the memory, and it is indicated in the translation table that at least one logical address for the particular data is associated with the data pattern.

Abstract: A hierarchy of multiple levels of storage resources and associated QOS (quality of service) limits and buckets of tokens may be specified. A different QOS limit may be applied to each individual storage resource. The buckets may denote current amounts of tokens available for consumption in connection with servicing I/O operations. Each bucket may denote a current amount of available tokens for a corresponding storage resource of included in the hierarchy. Processing may include receiving a first I/O operation directed to a first storage resource, and determining, in accordance with the buckets of available tokens, whether to service the first I/O operation.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a speculative cache modification design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a cache communicably interfaced with the data bus; a pipeline communicably interfaced with the data bus, in which the pipeline is to receive a store instruction corresponding to a cache line to be written to cache; caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline; and cache line validation logic to determine if the cache line written into the cache is valid or invalid, in which the cache line validation logic is to invalidate the cache line speculatively written into the cache when determined invalid and further in which the store instruction is allowed to retire from the pipeline when the cache line is determined to be valid.

Abstract: The present invention provides a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management schemes. In the system, NVM is used as large-capacity main memory, and DRAM is used as a cache to the NVM. Some reserved bits in the data structure of TLB and last-level page table are employed effectively to eliminate hardware costs in the conventional hardware-managed hierarchical memory architecture. The cache management in such a heterogeneous memory system is pushed to the software level. Moreover, the invention is able to reduce memory access latency in case of last-level cache misses. Considering that many applications have relatively poor data locality in big data application environments, the conventional demand-based data fetching policy for DRAM cache can aggravates cache pollution.

Abstract: A system for extending life expectancy of disks in a cloud-based service system and the system using the method are disclosed. The present invention uses LSTM modeling and the k-means clustering algorithms to find out performance limit and target lifespan for a cluster of disks assigned for a specific workload running over the cloud-based service system. The disks can be predicted to have a minimum lifetime and the requirement of the workload can be satisfied. Meanwhile, the minimum lifetime is the longest life the disk can last.