Abstract: A method and apparatus for assembling a semiconductor device. A chip (901) with solder bodies (903) on its contact pads is flipped onto a substrate (904). After the reflow process, a gap (910) spaces chip and substrate apart. A polymer precursor is selected for its viscosity of known temperature dependence. The apparatus has a plate (800) with heating and cooling means to select and control a temperature profile from location to location across the plate. After preheating, the assembly is placed on a mesa (801) of the plate configured to heat only a portion of the substrate. Movable capillaries (840, 921) blow cooled gas onto selected locations of the assembly. After the temperature profile is reached, a quantity of the precursor is deposited at a chip side and pulled into the gap by capillary action. The capillary flow is controlled by controlling the precursor viscosity based on the temperature profile, resulting in a substantially linear front, until the gap is filled substantially without voids.

Abstract: A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.

Abstract: A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a source/drain, an insulating layer, and a semiconductor active layer. The gate and the source/drain are respectively deposited on the substrate and are separated by the insulating layer on the substrate. The semiconductor active layer connects the source and the drain. The material of the semiconductor active layer is a semiconductor precursor which produces semiconductor property after being irradiated by a light source. A liquid crystal display which includes the above thin film transistor is also provided.

Abstract: Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.

Abstract: Illustrative methods, apparatuses and software are described for searching for an ID of a slave node within a communication network, such as a single-wire communication network. Also, illustrative embodiments of a master node and a slave node are described.

Abstract: Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may be used in a variety of electronic system applications. A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide provides a reliable gate dielectric with an equivalent oxide thickness thinner than attainable using SiO2.

Abstract: A semiconductor chip (1) comprises a p-doped region (I) having a cladding layer (18) and a contact layer (21) between which a first interlayer (19) and a second interlayer (20) are arranged. A concentration of a first material component (B) within the first and the second interlayer (19, 20) changes in such a way that the band gap varies in a range lying between the band gap of the cladding layer (18) and the band gap of the contact layer (21). A method for producing a semiconductor chip of this type is also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.

Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS, or biotechnology devices. The method includes application of a protective thin film which typically has a thickness ranging from about 3 ? to about 1,000 ?, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.

Abstract: There is provided a damage recovery method capable of recovering electrical characteristics of a low dielectric insulating film sufficiently while suppressing oxidation of buried metal and generation of pattern defaults. A damaged functional group generated in a surface of the low dielectric insulating film by a processing is substituted with a hydrophobic functional group (ST. 2). A damaged component present under a dense layer generated in the surface of the low dielectric insulating film by the substitution process is recovered by using an ultraviolet heating process (ST. 3).

Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

Abstract: A method for depositing fine particles from a suspension on selected regions of a substrate is disclosed. The particles are deposited on selected regions of a clean hydrophobic semiconductor surface that are surrounded by a wetting boundary which includes a mesa formed by etching through a silicon-on-insulator (SOI) film and an underlying buried oxide of an SOI substrate. The process is well suited for the growth of semiconductor nanowires that nucleates from fine particle used as a catalyst.

Abstract: A formation in a first surface of a substrate is machined by an ultraviolet or visible radiation laser, to a predetermined depth that is less than a full depth of the substrate; and material is removed from a second surface of the substrate opposed to the first surface to the predetermined depth from the first surface to communicate with the formation. Material may be removed by, for example, lapping and polishing, chemical etching, plasma etching or laser ablation. The invention has application in, for example, dicing semiconductor wafers to forming metallised vias in wafers.

Abstract: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

Abstract: An alloy forming dopant material is deposited prior to the formation of a copper line, for instance by incorporating the dopant material into the barrier layer, which is then driven into the vicinity of a weak interface by means of a heat treatment. As indicated by corresponding investigations, the dopant material is substantially transported to the weak interface through grain boundary regions rather than through the bulk copper material (copper grains), thereby enabling moderately high alloy concentrations in the vicinity of the interface while maintaining a relatively low overall concentration within the grains. The alloy at the interface reduces electromigration along the interface.

Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.

Abstract: A locking plate fast fastening ceiling fan blades is provided where several nicks are formed, and a thru hole is formed communicating with the open side of one of the nicks. A wedge unit is provided in the thru hole of the locking plate. Thus, when a blade is installed on the blade rack, only the blade is set around the pillars of the blade rack, then the locking plate is made to wedge to the pillar of blade rack, and the wedge unit is made to stay close to and pass through the pillar in the nick communicating with the thru hole for fast and exact completion of fixing of the blade onto the blade rack.

Abstract: The present invention relates to a method of forming a flash memory device, which is capable of forming floating gates. According to a method of forming a flash memory device in accordance with the present invention, isolation mask patterns are first formed over a semiconductor substrate. Trenches are formed by performing an etching process using the isolation mask patterns. Isolation layers are formed between the isolation mask patterns, including the insides of the respective trenches. The isolation mask patterns are removed. Tunnel dielectric layers and crystallized first conductive layers are sequentially formed over the exposed semiconductor substrate. A dielectric layer and a second conductive layer are formed over the isolation layers and the first conductive layers.

Abstract: A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls.