Abstract: Providing an image combination device and/or a display system comprising the same. The image combination device including an SGL control unit separating a plurality of layers into a first group layer and a second group layer not overlapping the first group layer, and a multi-layer blender combining the first group layer to produce a first composite image in a first frame and combining the second group layer including updated layers with the first composite image of the first frame to produce a second composite image in a second frame subsequent to the first frame.

Abstract: A retrieval apparatus includes a processor and a memory and retrieves a condition given to a semiconductor treatment apparatus. The processor receives a processing result of a semiconductor, a condition corresponding to the processing result, a target value for treating the semiconductor, and a retrieval region. A prediction model is generated indicating a relationship between the condition and the processing result based on a set value of the condition in the retrieval region, and the processing result; calculates a predicted value, performs a demonstration test, acquires an actually measured value, outputs the predicted value as a set value when the actually measured value reaches the target value. When the actually measured value does not reach the target value, the prediction model is updated by applying the predicted value and the actually measured value to the set value and the processing result, respectively.

Abstract: A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.

Abstract: A method for increasing the speed of a bipolar transistor, includes the following steps: providing a bipolar transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, base, and collector regions; and adapting the base region to enhance stimulated emission to the detriment of spontaneous emission, so as to reduce carrier recombination lifetime in the base region.

Abstract: A level shifter (1) that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. Level shifter (1) may include a transistor (P101) providing a controllable current path between a voltage terminal (3) and an output signal (TOUT) based on the logic level of an input signal (IN). Series connected transistors (P104 and P105) may provide a controllable current path between voltage terminal (3) and output signal (TOUT) based on the logic level of an input signal (IN). Transistor (P105) may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width (WT) may be adjusted in accordance with a mode of operation and a transition time of output signal (TOUT) may be improved.

Abstract: A low-cost, novel electrically erasable programmable read only memory cell array. The EEPROM memory cell array includes a well of P− type conductivity. A first well of N-type conductivity resides within the well of P− type conductivity. A second well of N-type conductivity residing within the well of P− type conductivity spaced apart from the first well of N-type conductivity. A plurality of wells of P+ type conductivity reside within the second well of N-type conductivity. A plurality of contacts coupling a plurality of bit lines to the plurality of wells of P+ type conductivity. A third well of N-type conductivity resides within the well of P− type conductivity and is spaced apart from the first well of N-type conductivity and the second well of N-type conductivity. A single polysilicon layer disposed over the first well, the second well, and the third well.

Abstract: An electronic circuit device is provided which can avoid unnecessary spreading of a sealing resin and on which components can be mounted at a high mounting density. An enclosure for preventing the resin from flowing outside its intended boundaries and having a larger size than a chip in a chip mounting area of a circuit board is formed. The chip is mounted in a face-down orientation in the chip mounting area enclosed by the enclosure. A sealing resin is cast through a gate for casting a resin and introduced into the gap between the chip and the circuit board. It can be judged whether the charging of the resin has been completed or not, by checking the flowing of the resin into the groove.

Abstract: Semiconductor chips, such as photosensor arrays in a full-width scanner, are mounted on printed wiring boards. The printed wiring boards are in turn mounted on a second layer of printed wiring board material. The two layers of printed wiring board material are attached so that the seams between adjacent printed wiring boards in each layer alternate in a brick-like fashion. This structure enables arrays of semiconductor chips to be constructed in relatively long lengths, with minimal risk of damage caused by thermal stresses.

Abstract: First to fourth power wiring conductors and first to fourth ground wiring conductors are arranged on first to fourth insulating layers, respectively, and a first signal wiring conductor is arranged on the first or second insulating layer and a second signal wiring conductor is arranged on the third or fourth insulating layer.