Abstract: A method is provided for collaborative caching between a server cache (104) of a server computer (102) and an array cache (112) of a storage array (110) coupled to the server computer. The method includes collecting instrumentation data on the server cache and the array cache of the storage array and, based on the instrumentation data, adjusting the operation of at least one of the server cache and the array cache.

Abstract: An information processing apparatus includes a detecting unit that detects a capacity of a free space of a non-volatile storage device in an apparatus including the non-volatile storage device and a volatile storage device, a determining unit that determines whether the setting of notification destination information to the non-volatile storage device is available on the basis of the detected capacity, an information setting unit that sets the notification destination information to the volatile storage device when the determining unit determines that the setting of the notification destination information to the non-volatile storage device is not available, and an interval setting unit that sets an interval of communication for management with the apparatus to be shorter than that set when it is determined that the setting of the notification destination information is available, if the determining unit determines that the setting of the notification destination information is not available.

Abstract: A copy control apparatus includes a processor. The processor is configured to record, in update location information, an update count for each of sectional areas obtained by sectioning a copy-source area. The update count indicates a number of updates of data in a sectional area. The update count is indicative of more than two values. The processor is configured to perform first copy of copying data in the copy-source area to a copy-destination area based on the update location information. The processor is configured to deter the first copy for data in a sectional area for which an update count indicating more than a predetermined number is recorded in the update location information.

Abstract: A data processing systems employing a coherent memory system comprises multiple main cache memories. An inclusive snoop directory memory stores directory lines. Each directory line includes a directory tag and multiple snoop vectors. Each snoop vector relates to a span of memory addresses corresponding to the cache line size within the main cache memories.

Abstract: Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system writes data to a physical location of a memory and stores the physical location of the memory in a Flash Management Unit Tag cache (“Tag cache”). The controller identifies a data keep cache that is associated with the physical location of memory and updates an XOR sum stored in the identified data keep cache. The controller determines whether to perform a verification operation, and in response to a determination to perform the verification operation, verifies data stored at each physical location that has been stored in the Tag cache since a previous verification operation. Additionally, the controller determines whether to perform a reset operation, and in response to a determination to perform the reset operation, flushes the Tag cache and the plurality of data keep caches.

Abstract: A memory system for transmitting data to and receiving data from a host apparatus includes a semiconductor memory and an access-controlling part. The semiconductor memory has storage areas identified by physical addresses, stores data in each of the storage areas, performs data write in accordance with a request made by the host apparatus. The access-controlling part selects a recommended address, which is recommended to be used in a next data write, on the basis of operation information about a factor that influences time consumed for data write in the semiconductor memory, and outputs the recommended address to the host apparatus.

Abstract: A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data updating and helps reduce program disturb of the memory cells of the non-volatile memory device. The various embodiments utilize a version number associated with each erase block, data block, sector, and/or cluster. This allows for determination of currently valid data block, sector and/or cluster associated with the logical ID of the data grouping by locating the most recent version associated with the logical ID. With this approach, old data need not be invalidated by programming a valid/invalid flag, avoiding the risk of program disturb in the surrounding data rows.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: A disk array apparatus has a plurality of the same type of disk array units. Each of the disk array units has a plurality of storage areas in each of which firmware for allowing the disk array unit to operate is stored. When the disk array apparatus recognizes that a first disk array unit has been disposed therein, it compares a version number of firmware stored in each storage area included in the first disk array unit with a version number of firmware stored in each storage area included in a second disk array unit that currently operates in the disk array apparatus. If these version numbers are the same, the disk array apparatus makes a storage area in which firmware executed by the first disk array unit is stored conform to a storage area in which firmware executed by the second disk array unit is stored.

Abstract: A memory leveling system updates physical memory blocks, or blocks, to maintain generally even wear. The system maintains an update count for each block, incrementing a wear level count when the update count reaches a wear level threshold. The system compares a wear level of blocks to determine whether to update a block in place or move data on the block to a less-worn physical block. The system groups the blocks into wear level groups identified by a common wear level to identify blocks that are being worn at a faster or slower than average rate. If an empty block count of a least worn group drops below a threshold, the system moves data from one of the blocks in the least worn group to an empty block in a most worn group.

Abstract: Provided are a method, system, and article of manufacture for managing write requests to data sets in a primary volume subject to being copied to a secondary volume. Information indicating data sets to copy from a primary storage to a secondary storage is generated. A write request is received to write data to a target data set indicated in the information to copy from the primary storage to the secondary storage. A determination is made as to whether the write request is part of a sequential write access. The target data set and sequential data sets following the target data set are copied from the primary storage to the secondary storage. The write request to write the data to the primary storage is executed in response to receiving acknowledgment that the target data set was copied to the secondary storage.

Abstract: A register having a security function is provided. The register includes: a write security unit and a storage unit. The write security unit outputs a first control signal to control whether a write operation is permissible, in response to a write signal, an address signal, and a write permission signal. The storage unit writes and stores input data, in response to the first control signal. The write permission signal is received from an external source and indicates whether to protect the written data.

Abstract: In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cache hierarchy in a remote coherency domain a domain indication scrubbing request targeting a target memory block that may be cached by the at least one cache hierarchy. In response to receipt of a coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.