Patents Examined by Thanhha Pham
  • Patent number: 10236324
    Abstract: A full-color light emitting diode (LED) display having an improved luminance is provided herein. More specifically, provided herein are a full-color LED display, in which an amount of light blocked by electrodes and not extracted is minimized and ultra-small LED devices are connected to ultra-small electrodes without defects such as electrical short circuits and the like, wherein the full-color LED display exhibits a further improved luminance when a direct current (DC) driving voltage is used and each pixel of the full-color LED display exhibits uniform luminance when the DC driving voltage is used, and a method of manufacturing the same.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: March 19, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Rag Do, Yun Jae Eo, Yeon Goog Sung
  • Patent number: 10217847
    Abstract: A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 26, 2019
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10217767
    Abstract: A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sung Ho Kim, Dong Won Kim, Jong Moo Huh
  • Patent number: 10211054
    Abstract: Embodiments of the invention are directed to methods and resulting structures for forming a storage element using phase change memory (PCM). In a non-limiting embodiment of the invention, a PCM layer is formed over a surface of a bottom electrode. A top electrode is formed over the PCM layer using a tone inversion process that includes a sacrificial layer. A PCM pillar is then formed by patterning the PCM layer to expose a surface of the bottom electrode. The tone inversion process enables a sub-50 nm PCM pillar diameter.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew J. BrightSky, Robert L. Bruce, John M. Papalia, HsinYu Tsai
  • Patent number: 10192775
    Abstract: Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 29, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Ludovic Godet, Rui Cheng, Erica Chen, Ziqing Duan, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 10192973
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Ha-Young Jeon, Byung-Kwon Cho, Jeong-Nam Han
  • Patent number: 10192976
    Abstract: An exemplary quantum dot device can be provided, which can include, for example, at least three conductive layers and at least two insulating layers electrically insulating the at least three conductive layers from one another. For example, one of the conductive layers can be composed of a different material than the other two of the conductive layers. The conductive layers can be composed of (i) aluminum, (ii) gold, (iii) copper or (iv) polysilicon, and/or the at least three conductive layers can be composed at least partially of (i) aluminum, (ii) gold, (iii) copper or (iv) polysilicon. The insulating layers can be composed of (i) silicon oxide, (ii) silicon nitride and/or (iii) aluminum oxide.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: January 29, 2019
    Assignee: The Trustees of Princeton University
    Inventors: Jason Petta, David Zajac, Thomas Hazard
  • Patent number: 10192883
    Abstract: A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the ceil region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Hwan Son, Young Woo Park, Jae Duk Lee
  • Patent number: 10191345
    Abstract: A display device is disclosed, which includes: a first substrate; a first transistor disposed on the first substrate, wherein the first transistor comprises a first semiconductor layer; a second transistor disposed on the first substrate, wherein the second transistor includes a second semiconductor layer; and a first insulating layer disposed under the first semiconductor layer; wherein a thickness of the first insulating layer is greater than or equal to 200 nm and less than or equal to 500 nm; and wherein one of the first semiconductor layer and the second semiconductor layer comprises a silicon semiconductor layer, and the other comprises an oxide semiconductor layer.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: January 29, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Chandra Lius, Kuan-Feng Lee, Nai-Fang Hsu
  • Patent number: 10186623
    Abstract: An integrated circuit that includes a substrate, a photodiode, and a Fresnel structure. The photodiode is formed on the substrate, and it has a p-n junction. The Fresnel structure is formed above the photodiode, and it defines a focal zone that is positioned within a proximity of the p-n junction. In one aspect, the Fresnel structure may include a trench pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In another aspect, the Fresnel structure may include a wiring pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In yet another aspect, the Fresnel structure may include a transparent dielectric pattern that functions as a refractive means for redirecting and concentrating incident photons to the focal zone.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: January 22, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Debarshi Basu, Henry Litzmann Edwards, Ricky A. Jackson, Marco A. Gardner
  • Patent number: 10186576
    Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raja Selvaraj, Anant Shankar Kamath, Byron Lovell Williams, Thomas D. Bonifield, John Kenneth Arch
  • Patent number: 10186552
    Abstract: A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seol Choi, Hideki Horii, Dong-ho Ahn, Seong-geon Park, Dong-jun Seong, Min-kyu Yang, Jung-moo Lee
  • Patent number: 10177066
    Abstract: A thermal management solution may be provided for a microelectronic system including a flexible integrated heat spreader, wherein the flexible integrated heat spreader may comprise a plurality of thermally conductive structures having a flexible thermally conductive film attached to and extending between each of the plurality of thermally conductive structures. The flexible integrated heat spreader may be incorporated into multi-chip package by providing a microelectronic substrate having a plurality of microelectronic devices attached thereto and by thermally contacting each of the plurality of thermally conductive structures of the flexible integrated heat spreader to its respective microelectronic device on the microelectronic substrate.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Ameya Limaye, Shubhada Sahasrabudhe
  • Patent number: 10177148
    Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Ha, Byoung-Hak Hong
  • Patent number: 10163973
    Abstract: A method for forming an FSI image sensor device structure is provided. The method includes forming a pixel region in a substrate and forming a dielectric layer over the substrate. The method includes forming a trench through the dielectric layer, and the trench includes a top portion and a bottom portion, and the trench is directly above the pixel region. The method includes forming a protection layer in the bottom portion of the trench and enlarging a top width of the top portion of the trench, and the trench has a wide top portion and a narrow bottom portion. The wide top portion has top sidewall surfaces, the narrow bottom portion has bottom sidewall surfaces, and the top sidewall surfaces taper gradually toward the bottom sidewall surfaces. The method includes filling a transparent dielectric layer in the trench to form a light pipe.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Kuei Chang, Keng-Yu Chou, Jen-Cheng Liu, Jeng-Shyan Lin
  • Patent number: 10163734
    Abstract: A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Chih-Fan Huang, Chun-Hung Lin, Ming-Da Cheng, Chung-Shi Liu, Mirng-Ji Lii
  • Patent number: 10164063
    Abstract: The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate layer over the first portion and the second portion of the protection layer. The method for forming a semiconductor structure further includes patterning the dummy gate layer to form a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Chiang, Po-Hsiung Leu, Ding-I Liu
  • Patent number: 10164060
    Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Junli Wang, Yongan Xu, Yunpeng Yin
  • Patent number: 10147803
    Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Junli Wang, Yongan Xu, Yunpeng Yin
  • Patent number: 10141309
    Abstract: CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek