Patents Examined by Thanhha S. Pham
  • Patent number: 10734560
    Abstract: A device for an LED has a substrate and a circuit on the substrate configured to accept the LED. The circuit includes a first set of electrical traces terminating at a first set of solder pads for a first sized LED, a second set of electrical traces terminating at a second set of solder pads for a second sized LED different from the first sized LED, and peripheral electrical traces for electrically interconnecting electrical traces of the first set of electrical traces or between electrical traces of the second set of electrical traces. Connection components electrically interconnect the first set of electrical traces with each other or the electrical traces of the second set of electrical traces with each other, respectively, at corresponding solder pads. The device is configurable to provide a first voltage and a second voltage to the LED.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 4, 2020
    Assignee: Cree, Inc.
    Inventors: David N. Randolph, Ryan C. Mohn
  • Patent number: 10727290
    Abstract: An active-matrix display device includes pixels arranged in a matrix, and each of the pixels includes subpixels that are arranged along an X direction and emit light of mutually different colors. Each of the subpixels includes a TFT element provided on a TFT substrate and an organic EL element provided on the TFT substrate. The organic EL element has an opening which is a region from which emitted light exits, and the TFT substrate includes a first layer and a second layer. When same-colored subpixels of two of the pixels adjacent in the X direction are seen in a plan view, the first layer has a portion arranged in line symmetry between the same-colored subpixels and the second layer is disposed at an identical position in the openings of the same-colored subpixels.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 28, 2020
    Assignee: JOLED INC.
    Inventor: Tetsuro Yamamoto
  • Patent number: 10727244
    Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Joon-Sung Lim, Eunsuk Cho
  • Patent number: 10714412
    Abstract: A semiconductor package includes a leadframe comprising input/output pins accessible external to the semiconductor package and a semiconductor die electrically connected to the leadframe. The semiconductor package also includes a passive electrical component mounted on a side of the semiconductor die opposite the leadframe. Mold compound encapsulates the passive electrical component, semiconductor die, and leadframe to form the semiconductor package. Associated methods are disclosed as well.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joyce Marie Mullenix, Roberto Giampiero Massolini, Rajeev D. Joshi
  • Patent number: 10714626
    Abstract: The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film. An insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is further formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. The oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by removing impurities such as hydrogen, moisture, a hydroxyl group, and hydride from the oxide semiconductor and supplying oxygen which is a major constituent of the oxide semiconductor and is simultaneously reduced in a step of removing impurities.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10707337
    Abstract: A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 7, 2020
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Samuel Menard
  • Patent number: 10700023
    Abstract: Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 30, 2020
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventor: Timothy Gittemeier
  • Patent number: 10699973
    Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDERS INC.
    Inventors: Anthony K. Stamper, Patrick S. Spinney, Jeffrey C. Stamm
  • Patent number: 10692889
    Abstract: The present invention is related to a field of display technology, and in particular to a thin film transistor array substrate, which comprises a glass substrate, as well as a buffer layer and a pixel structure layer disposed on a first surface of the glass substrate, wherein a plurality of patterned three-dimensional microstructures are formed on the first surface of the glass substrate, and the buffer layer and the first surface are mutually meshed. The present invention also discloses a method of manufacturing the array substrate mentioned above, and a display device comprising the array substrate. The thin film transistor array substrate provided by the present invention improves the light transmittance of the array substrate.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 23, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Guowei Zha
  • Patent number: 10692874
    Abstract: A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 23, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Wu-Yi Chien
  • Patent number: 10690786
    Abstract: A X-ray detector includes: a base substrate; a plurality of detection modules disposed on the base substrate, wherein the detection module includes a thin film transistor disposed on the base substrate, an insulating layer with a via hole disposed on the thin film transistor and a photosensitive structure disposed on the insulating layer, a first electrode of the thin film transistor is electrically connected to the photosensitive structure through the via hole on the insulating layer, and the first electrode is a source or a drain electrode of the thin film transistor; and a scintillation layer disposed on the detection module. In the present disclosure, by disposing the photosensitive structure and the TFT in different layers, the photosensitive area of the photosensitive structure is enlarged, and it will not be affected by the TFT.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 23, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hui Tian
  • Patent number: 10661394
    Abstract: Disclosed is a metal core solder ball having improved heat conductivity, including a metal core having a diameter of 40˜600 ?m, a first plating layer formed on the outer surface of the metal core, and a second plating layer formed on the outer surface of the first plating layer.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 26, 2020
    Assignee: DUKSAN HI-METAL CO., LTD.
    Inventors: Yong Cheol Chu, Hyun Kyu Lee, Jung Ug Kwak, Seung Jin Lee, Sang Ho Jeon, Yong Sik Choi
  • Patent number: 10658332
    Abstract: A stack package includes a second sub-package stacked on a first sub-package. The stack package also includes a plurality of dummy balls located between the first and second sub-packages to support the second sub-package. Each of the first and second sub-packages includes a semiconductor die and a bridge, die which are spaced apart from each other.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Jong Hoon Kim
  • Patent number: 10651227
    Abstract: An array substrate for an X-ray detector and an X-ray detector including the reduces or minimizes a leakage current caused by etching of a PIN layer, and also reduces or minimizes light reaction of the PIN layer within a non-pixel region. The array substrate for the X-ray detector includes an integrated PIN layer formed to cover all pixel regions. Upper electrodes, which are spaced apart from each other according to individual pixel regions, are disposed over the PIN layer. A light shielding portion is disposed between neighboring upper electrodes.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 12, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Jungyul Yang
  • Patent number: 10636731
    Abstract: Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using mechanically flexible interconnects, and the like.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 28, 2020
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Paul Kim Jo
  • Patent number: 10629474
    Abstract: Various capacitive isolation structures which can be readily incorporated into existing IC manufacturing procedures. An illustrative method embodiment for forming an isolation capacitance includes: (a) forming a recess on a surface of an integrated circuit substrate, the recess having a bottom surface; (b) coating the bottom surface with an insulating layer; (c) overlaying a bottom electrode on the insulating layer; (d) filling the recess with a bulk insulator having a minimum thickness no less than half a depth of the recess; and (e) depositing a top electrode above the bulk insulator.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 21, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: YongZhong Hu
  • Patent number: 10622436
    Abstract: A display device includes: an initialization power line extending along a first direction; a scan line extending along the first direction and spaced apart from the initialization power line, a data line and a driving voltage line insulated from the initialization power line and the scan line and extending along the second direction; a first switching element including a first electrode connected to the driving voltage line, a first gate electrode overlapping the initialization power line, and a second electrode; a second switching element including a third electrode connected to the first gate electrode, a second gate electrode connected to the scan line, and a fourth electrode; a third switching element including a fifth electrode connected to the fourth electrode, a third gate electrode connected to the initialization power line, and a sixth electrode connected to the second electrode; and a light emitting element connected to the second electrode.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Hyun Park, Cheol Gon Lee, Chong Chul Chai, Yang Hwa Choi
  • Patent number: 10608116
    Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 31, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10586760
    Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The outer sidewalls of the upper portion of the casing are located between vertical planes defined by opposing outer sidewalls of the lower portion of the casing.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, Thomas Brunschwiler, Bruno Michel
  • Patent number: 10586825
    Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material to convert image light into image charge, and a metal grid, including a metal shield that is coplanar with the metal grid, disposed proximate to a backside of the semiconductor material. The metal grid is optically aligned with the plurality of photodiodes to direct the image light into the plurality of photodiodes, and a contact pad is disposed in a trench in the semiconductor material. The contact pad is coupled to the metal shield to ground the metal shield.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 10, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Qin Wang, Gang Chen, Duli Mao