Abstract: A memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.

Abstract: A method is presented for forming a cell structure. The method includes constructing a resistive random access memory (RRAM) device, constructing a phase change memory (PCM) device in series with the RRAM device such that one of the electrodes of the PCM device is connected to a reactive electrode of the RRAM device, and connecting a complementary metal oxide semiconductor (CMOS) inverter to the RRAM and PCM devices to individually control switching behaviors of the RRAM and PCM devices.

Abstract: A semiconductor apparatus includes a first memory, a second memory, and a shared reference resistor. The first memory is electrically coupled to the shared reference resistor, and the second memory is also electrically coupled to the shared reference resistor. Each of the first and second memories performs a basic calibration operation thereof by selectively using the shared reference resistor in response to a clock signal, and a mirror function signal, which has different logic levels according to which memory between the first and second memories performs calibration operations.

Abstract: A capacitance coupled to a memory node and a word line of an SRAM cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a LOW level) and the memory node retains a HIGH level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the LOW level) and the memory node retains the LOW level.