Abstract: A method of manufacturing an inorganic nanotube using a carbon nanotube (CNT) as a template, includes preparing a template on which a CNT or a CNT array is formed, forming an inorganic thin film on the CNT by depositing an inorganic material on the template using atomic layer deposition (ALD), and removing the CNT to obtain an inorganic nanotube or an inorganic nanotube array, respectively.

Abstract: In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate.

Abstract: There is disclosed a method for forming micro patterns in a semiconductor integrated circuit device with high productivity and high accuracy. A photolithography having high throughput and electron beam lithography using a reticle and having relatively high throughput and high resolution are selectively used so as to obtain highest throughput while satisfying accuracy and resolution required for each product/layer. In the case of using the electron beam lithography, a non-complementary reticle and a complementary reticle are selectively used so as to obtain highest throughput while satisfying required accuracy and resolution. Thus, productivity and integration can be improved for the semiconductor integrated circuit device.

Abstract: A process for manufacturing a wafer from a layer of material such as silicon and having a multiplicity of MEMS devices such as mirrors with gimbals formed thereon is disclosed. The features of the devices on the wafer as well as the boundaries which separate individual devices are defined by lines having a constant width so as to avoid microloading effects. Waste areas of the layer of material which are greater than the constant line width are removed as breakout pieces during the release process.

Abstract: An emission system for presenting visual image is disclosed. The emissive system typically contains first electrodes deposited over and in contact with a substrate. One or more conjugated organic buffer layers are then deposited over and in contact with the first electrodes, and second electrodes are subsequently deposited over the conjugated organic buffer layers. The conjugated organic buffer layers regulate current flow between the first electrodes and the second electrodes. Either before or after the deposition of each conjugated organic buffer layer, but before the deposition of the second electrodes, conjugated organic deposits are ink-jet printed such that they are in contact with at least one conjugated organic buffer layer. The conjugated organic deposits help to generate an indicator when a voltage stimulus is applied across the first electrodes and the second electrodes.

Abstract: A method of fabricating a semiconductor device that makes it possible to decrease the thermal resistance of the semiconductor device is provided. First, a semiconductor base layer is formed over a main surface of a semiconductor substrate. Then, the semiconductor base layer on which the at least one device structure has been formed is separated from the main surface of the semiconductor substrate. Further, the semiconductor base layer on which the at least one device structure has been formed and separated from the main, surface of the semiconductor substrate is attached onto a main surface of a diamond substrate. Finally, the semiconductor base layer thus attached is fixed to the main surface of the diamond substrate. The semiconductor base layer is preferably formed over the main surface of the semiconductor substrate through an intervening sacrificial layer. Also, the semiconductor base layer is separated from the main surface of the semiconductor substrate by removing the sacrificial layer.

Abstract: A second interlayer film is etched by an etching gas including fluorocarbon gas after a switch box is switched so that high frequency electricity is applied to an upper electrode. Then, the switch box is switched so that low power electricity is applied only to a lower-electrode/wafer-holder to generate plasma with using only fluorocarbon gas. The generated plasma etches a first interlayer film, and fluorine radicals dissociated from the fluorocarbon removes a hardened resist surface layer. It realizes etching with less damage on bases, because energy of incident ions is low.

Abstract: The invention describes an embedded dynamic random access memory (DRAM) fabrication method. After several landing pads in the memory cell region of a substrate have been formed, a bit-line contact opening and first contact opening are formed simultaneously. The bit-line contact opening exposes the landing pad and the first contact opening exposes the NMOS of the periphery circuit region. An N-type ion implantation is performed to implant N-type ions into the landing pad the NMOS. After a bit-line contact, a first contact, and a bit-line have been formed, a storage node contact opening and a second contact opening are formed simultaneously. The storage node contact opening exposes another landing pad and the second contact opening exposes a P-type MOS in the periphery circuit region. A P-type ion implantation step is conducted to implant P-type ions into the landing pad and the PMOS exposed by the second contact opening.

Abstract: A semiconductor device having a capacitor, a bipolar transistor and complementary MOSFETs on a semiconductor substrate, the capacitor being constituted from a first electrode 8, a second electrode 13 separated from the first electrode by an insulating film 11 and a third electrode 15 separated from the second electrode by another insulating film 14 and connected to the first electrode is manufactured; where all electrodes in the capacitor and insulating films between them are formed simultaneously with other manufacturing steps of a bipolar transistor or the MOSFETs. This manufacturing method can produce a semiconductor device such as a Bi-CMOS and the like, which is capable of large scale integration and has a capacitor with a large capacitance but occupying only a small area, with a high efficiency and a low cost.

Abstract: A method for transferring of individual devices or circuit elements, fabricated on a semiconducting substrate, to a new substrate and placing said devices and elements in predetermined locations on the new substrate. The method comprises shaping the devices and circuits as truncated cones, lifting them off the original semiconducting substrates and depositing them en masse onto the new substrate, followed by their placing into receptors on the new substrate. The new substrate has preliminarily made receptors in a form of a truncated cone and the devices and circuits fill these receptors. Both the receptors and the devices and circuits have metallization contacts enabling to establish electrical contact between them. A method for real-time monitoring and verification of correctness of placement of the devices and circuits into the receptors by applying voltage pulse waveforms and measuring the resulting current pulse.