Abstract: Silicon carbide devices and methods of fabricating silicon carbide devices are provided by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed-over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate.

Abstract: J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) are each connected to a respective second semiconductor region (5, 6). The first and second semiconductor regions (2, 3, 5, 6) are of opposite conductivity types. The second semiconductor regions (5) connected to the second contacts (9) extend in the first semiconductor region (2, 3) below the second semiconductor region (6) that is connected to the first contact (7), with the result that the three second semiconductor regions (5, 6) at least partially overlap in a projection onto a horizontal plane and a channel region (11) is formed between the three second semiconductor regions (5, 6) in the first semiconductor region (2, 3).

Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.

Abstract: A semiconductor device is disclosed including an IGFET (insulated gate field effect transistor) and a method of manufacturing the same. The semiconductor device may include an oxide film (115) or a nitride film (106) provided on a side surface of a gate electrode in such a manner that an overhang condition may not occur. In this way, operating characteristics of the IGFET may not be deteriorated and voids may not appear in filling regions of an interlayer insulating film so that isolation characteristics may not be deteriorated.

Abstract: The present invention provides a molecular device including a source region and a drain region, a molecular medium extending there between, and an electrically insulating layer between the source region, the drain region and the molecular medium. The molecular medium in the molecular device of present invention is a thin film having alternating monolayers of a metal—metal bonded complex monolayer and an organic monolayer.

Abstract: A first conductive layer of metal silicide, a silicon layer, an insulating layer, and a second conductive layer of metal or metal silicide are deposited in the order named on a surface of a a semiconductor substrate. Thereafter, the second conductive layer and the insulating layer are patterned to expose the silicon layer. The exposed silicon layer and the first conductive layer are patterned, thereby forming an MIM capacitance circuit.

Abstract: A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insulating material may be any suitable material including and not limited to one or a combination of materials such as BPSG, PSG, silicon dioxide and silicon nitride. The insulating layer is relatively thin and does not extend deeply into the gate trench, thereby reducing capacitance.

Abstract: A method of manufacturing an insulating film in a semiconductor device is disclosed. The method comprises the steps of forming a SOD film on the entire structure to fill any distance between conductive layer patterns and after performing a curing process, forming a hard mask film on the SOD film, wherein the silicon oxide film is deposited by plasma deposition method using SiH4 and N2O as a reaction gas at a low-temperature and at a low-pressure and wherein in a stabilization step, the supply amount of SiH4 is greater than that of N2O and in a deposition step, the supply amount of N2O is greater than that of SiH4.

Abstract: In a semiconductor device, a wiring line layer is formed on a substrate. A dielectric constant film is formed on the wiring line layer. An upper protection film is formed on an entire portion of the dielectric constant film. An opening portion is formed through the upper protection film and the dielectric constant film to the wiring line layer. A conductor buried portion formed into the opening portion. The dielectric constant film has a smaller dielectric constant value than those of a silicon oxide film and silicon nitride film. Also, a side protection film may be formed on all side portions of the opening portion.

Abstract: A method for forming an insulator film at a semiconductor temperature of 600° C. or less comprises the steps of forming a first insulator film by oxidizing a surface of a semiconductor in an atmosphere containing oxygen atom radicals, and forming a second insulator film on the first insulator film by deposition without exposing the first insulator film to outside air.

Abstract: The present invention provides a method for forming a silica-containing film with a low-dielectric constant of 3 or less on a semiconductor substrate steadily, which comprises steps of (a) applying a coating liquid for forming the silica-containing film with the low-dielectric constant onto the semiconductor substrate, (b) heating the thus coated film at 50 to 350° C., and then (c) curing the thus treated film at 350 to 450° C. in an inert-gas atmosphere containing 500 to 15,000 ppm by volume of oxygen, and also provides a semiconductor substrate having a silica-containing film formed by the above method. The above step (b) for the thermal treatment is preferably conducted at 150 to 350° C. for 1 to 3 minutes in an air atmosphere. Also, the above curing step (c) is preferably conducted by placing the semiconductor substrate on a hot plate kept at 350 to 450° C.

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device.

Abstract: An organic electroluminescent device having a luminescent layer interposed between an anode and a cathode, on a substrate, wherein a layer containing an electron-accepting compound containing a boron atom represented by the following formula (I): wherein each of Ar1 to Ar3 which are independent of one another, is an aromatic hydrocarbocyclic group or aromatic heterocyclic group which may have a substituent, and a hole transport compound, is formed between the luminescent layer and the anode.

Abstract: A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

Abstract: A one-time programmable memory cell includes a fuse and an anti-fuse in series. The memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite, typically dominated by the relatively high resistance of the anti-fuse. In the written state, the resistance is infinite because the breakdown of the fuse resulting in an open circuit. The cell may be programmed by applying a critical voltage across the cell generating a critical current to cause the fuse to become open. When critical voltage is applied, this generally causes the anti-fuse to break down, which in turn causes a pulse of high current to be applied to the fuse. The states are detected by applying a read voltage across the memory cell. If the memory has not been programmed, then a measurable amount flows. Otherwise, no current flows.

Abstract: A method of making a light-emitting device comprises forming a first and second components. The first component has a first substrate, a first electrode on the first substrate, an organic layer on the first electrode, and a light-transmissive second electrode on the organic layer. The second component has a light-transmissive second substrate, and a light transmissive, electrically conductive layer on the second substrate. The first and second components are joined with the second electrode of the first component facing the conductive layer of the second component. An electrical contact is formed between the second electrode of the first component and the electrically conductive layer of the second component.

Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.

Abstract: The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.

Abstract: The invention provides a method of making a transistor. A gate dielectric layer is formed on a semiconductor substrate. A gate is formed on the dielectric layer, the gate having an exposed upper surface and exposed side surfaces. A first silicon nitride layer having a first thickness is deposited over the gate, for example over an oxide layer on the gate, at a first deposition rate. A second silicon nitride layer having a second thickness is deposited over the first silicon nitride layer at a second deposition rate, the second thickness being more that the first thickness and the second deposition rate being more than the first deposition rate. The first silicon nitrogen layer then has a lower hydrogen concentration. At least the second silicon nitride layer (or a silicon oxide layer in the case of an ONO spacer) is etched to leave spacers next to the side surfaces while exposing the upper surface of the gate and areas of the substrate outside the spacers.

Abstract: A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor substrate, a gate extraction electrode which extends in a direction perpendicular to the longitudinal direction of the gate and is commonly connected to the gates of the unit cells, a drain extraction electrode which is positioned at a side where the drain extraction electrode faces the gate extraction electrode via the unit, extends in a direction perpendicular to the longitudinal direction of the drain, and is commonly connected to the drains of the unit cells, a gate pad connected to the gate extraction electrode, and a drain pad connected to the drain extraction electrodes. The gate pads of adjacent transistor units are connected to each other by a gate extraction electrode connection wiring line having a resistor of 0.6 to 10 &OHgr;.