Abstract: A method of producing a top gate thin-film transistor in which an insulated gate structure (14) is formed over an amorphous silicon layer with upper gate conductor (16) directly over the gate insulator layers. The gate conductor is patterned to be narrower than a spacing to be provided between source and drain electrode contacts. Laser annealing of areas of the amorphous silicon layer (12) not shielded by the gate conductor (16) is carried out to form polysilicon portions. The gate insulator layers are formed as a gate insulator layer (14a,14b) of first refractive index, and an overlying surface insulator layer (14c) of second, lower, refractive index. The overlying surface insulator layer has been found to reduce fluctuations in the reflectance of the structure in dependence upon the specific thicknesses of the gate insulator layers. Therefore, the tolerances for the thicknesses of the gate insulator layers can be reduced whilst maintaining control of the laser annealing process.