Abstract: A technique for providing information about the relationship between circuits and the amounts of power consumed by the respective circuits to control a heat-sensitive circuit with higher accuracy is disclosed. A decoder (6a) causes an ALU power evaluation counter (7a) to count when a control code applied thereto is not an ALU control code. The ALU power evaluation counter (7a) counts the number of control codes which do not operate an ALU (5a). A multiplier (14) multiplies the output from the ALU power evaluation counter (7a) by a predetermined number to provide the result to an adder (10). The adder (10) adds the results from multipliers (14-16) together to store the result in a total power evaluation register (11). The smaller the value stored in the total power evaluation register (11), the greater the amount of heat generated. A DRAM refresh control circuit (12) shortens a refresh cycle so that a DRAM (13) is frequently refreshed.

Abstract: An apparatus for and method of coupling a number of data processing components onto a bus for communication amongst the components with a symmetric parallel multi-processing bus system architecture. The bus architecture is particularly applicable to micro computer systems for the interconnection of processing units, memories, and peripherals. The function of arbitration is distributed within the users of the bus permitting ease of coupling relatively slow and fast devices to the same bus. Bus access priority may be easily modified either semi-permanently or by way of rotation.