Abstract: A nonvolatile semiconductor memory device includes a plurality of floating gate type memory cell transistors having control gates. Word lines are integrally formed with the control gates, and boosting lines are self-aligned with the word lines. During programming, a first voltage is applied to a selected word line, and then a second voltage is applied to the boosting line over the selected word line. The voltage on the selected word line is then increased by capacitive coupling of the second voltage thereon, thereby programming at least one selected memory cell transistor. Therefore, a voltage lower than a program voltage is used on a selected word line, thereby reducing chip area and enhancing programming speed.

Abstract: A mask pattern applied to a peripheral portion of a wafer has an open/close ratio substantially the same as that in a central portion thereof and prepared according to a looser design rule than that for forming the central portion. The looser design rule has a high latitude for out-of-focus exposure and provides high resistance to pattern removal. Since the open/close ratios in the central portion and the peripheral portion of the wafer are substantially the same, variance in process accuracy due to a micro-loading effect can be prevented.