Patents Examined by Thomas Bilodeau
  • Patent number: 5834369
    Abstract: There are provided the steps of: forming a connection hole in an interlayer insulating film overlying a lower metal interconnection; forming a W plug in the connection hole; forming a first metal film and a second metal film over the interlayer insulating film and the W plug; forming an interconnection underlying film by using a photoresist mask with no alignment margin; and forming a diffusion preventing film made of a titanium fluoride or the like over the W plug, while etching away the exposed part of the first metal film. Reciprocal diffusion of tungsten and aluminum is prevented by the titanium fluoride or the like, thereby preventing the formation of an alloy having high electric resistivity.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: November 10, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomoyasu Murakami, Kousaku Yano
  • Patent number: 5420066
    Abstract: In accordance with the invention, after a crystal growth is carried out successively to produce at least a first conductivity type lower cladding layer, an active layer, a second conductivity type first upper cladding layer of AlGaAs having an AlAs composition ratio of 0.38 to 0.6, an etching stopper layer of AlGaAs having an AlAs composition ratio of more than 0.6, and a second conductivity type second upper cladding layer of AlGaAs having an AlAs composition ratio of 0.38 to 0.6, the second upper cladding layer is selectively etched using an etchant including an organic acid and hydrogen peroxide, thereby forming a ridge. As a result, a ridge-type semiconductor laser device which has a desirable laser structure and an oscillation wavelength below 830 nm can be produced easily with improved controllability and reproducibility.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: May 30, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihiro Shima, Takeshi Miura, Tomoko Kadowaki, Norio Hayafuji
  • Patent number: 5380671
    Abstract: The invention describes a non-trenched buried contact for local interconnections in VLSI devices and provides a method for forming the non-trenched buried contact. By using trenched isolation and a trench polysilicon gate structure the buried contact process can be implemented so that there are no unwanted trenches formed in the area of the buried contact. The invention permits excellent planarization of the device prior to pre-metal dielectric and metal deposition.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: January 10, 1995
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, D. Y. Wu