Abstract: The present invention leverages high-frequency interrupts and/or low priority threads to accurately determine which computing resources are available. This provides a computing asset (CPUs and/or software applications) with a means to accurately compensate for resource utilization in order to increase its performance. By utilizing the present invention, the computing asset can optimize its performance in a real-time, self-tuning manner. In one instance of the present invention, high intensity, low priority threads are initiated on available CPUs (logical and/or physical) to effectively replace a CPU's idle time with the low priority thread. This thread generally constitutes a computationally-intensive and/or a memory-intensive thread which permits a highly accurate performance measurement to be obtained for available CPU resources.

Abstract: A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the target circuit changes from a disabled state to enabled state, the supply of the clock signal to the target circuit starts in accordance with the system clock signal, and if a valid output instruction signal indicating timings of data output from the target circuit changes from the enabled state to disabled state, the supply of the clock signal is stopped after a lapse of a predetermined time period set externally. The clock control circuit for supplying the valid clock to the target circuit can therefore be used in common for a variety of waveforms of a valid input flag and a valid output flag.

Abstract: A dynamic memory buffer buffers between software applications executing on a processor and data generating and/or receiving devices in communication through the buffer with the applications. The buffer includes buffer manager for controlling allocation of one or more portions of the buffer to the applications so as to reduce power dissipation occurring within the devices.

Abstract: A processor capable of reducing power consumption of an electronic information device sends a frequency control signal to a clock oscillator, operates at a frequency in accordance with the frequency control signal. Further, the processor sends a voltage request signal to a power supply circuit, and operates at a voltage in accordance with the voltage request signal. The processor controls the supplied clock frequency and power supply voltage so that the processor itself operates in an operation area in which energy consumption becomes minimum for a predetermined amount of data. Such an operation area is defined by a clock frequency, a power supply voltage, and power supply efficiency (?) of the power supply circuit.

Abstract: The present invention relates to an integrated circuit comprising a central processing unit clocked by a clock signal, a main oscillator circuit supplying a first clock signal and a peripheral circuit supplying a periodic wake up signal, the central processing unit comprising a first operating mode at full power, in which the first clock signal is applied to the central processing unit, and an active halt mode in which the main oscillator circuit and the central processing unit are deactivated, the central processing unit being awakened by the periodic wake-up signal.

Abstract: An integrated circuit device provides an operational set point indicator. The operational set point indicator is utilized for obtaining a plurality of operational set points. Each of the plurality of operational set points can be a pair of an operational voltage and an operational frequency for application to the integrated circuit device. The operational set point indicator can be, for example, a Schmoo Class Register, a Device Identification Register, or actual operating condition information of the integrated circuit device. The Schmoo Class Register and the Device Identification Register are utilized to identify a performance state table in memory. The actual operating conditional information can be one or more entire Schmoo Plots for the device or a subset of such information. Operational set points are used during operation of the integrated circuit device, for example, in power management applications.

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract: Provided is a technique for power and performance management of one or more storage devices. With a power and performance management agent, a power change notification identifying a power set point is received and a power state of at least one storage device is adjusted.

Abstract: A method and system to create a recovery image of firmware stored in a firmware storage device of a computer system. A recovery image of firmware is created and stored at a target location, wherein the target location includes a magnetic disk. The firmware storage device to store Basic Input/Output System (BIOS) firmware and/or Non-Volatile Random Access Memory (NVRAM) Data of an Extensible Firmware Interface (EFI) compliant computer system. In one embodiment, the firmware of the computer system is recovered from the recovery image.

Abstract: A method, a device, and a bus system for synchronizing at least two TTCAN buses having at least one bus user, a global time being determined in each TTCAN bus, and the deviations in the global times of the TTCAN buses being determined from the global times, the TTCAN buses being connected via at least one user and the deviations in the individual global times being transmitted to at least one bus user, and the global times of the TTCAN buses connected via at least one user being adjusted to one another as a function of the deviations in the global times, so that the TTCAN buses are synchronized with respect to the global times.

Abstract: A programmable power management integrated circuit includes analog input monitors that receive analog input signals that correspond to voltage, current, or temperature measurements. The analog input monitors apply programmable thresholds to the measurements and output the results to a programmable logic device, which may generate various status and/or control signals to the system being monitored. The programmable logic device controls FET drivers that can switch on and off power to the monitored system. The programmable power management integrated circuit may also comprise an internal oscillator, a serial interface, an in-system programmable interface, a joint test action group interface, a memory that stores identification information, and a register for capturing system information during power-down.

Abstract: A method for adapting the periodicity of polling for pending service requests, by polling system devices for pending service requests, recording whether or not there was a pending service request and, based on accumulated data, determining whether or not the system devices are idle. Based on this determination, the system may elect to enter a power conservation mode until device activity is signaled, or an adjustable period of time elapses. The adaptation mechanism may alter the periodicity of the timer interrupt, disable or enable device interrupts, and modify variables used to determine system idleness (including minimum latency and minimum idleness thresholds). In this manner, the system can conserve power while maintaining system performance and responsiveness.

Abstract: Clock and data recovery circuitry is provided that is used in integrated circuits such as programmable logic device integrated circuits. The clock and data recovery circuitry may recover digital data and an embedded clock from a high-speed differential input data stream. The clock and data recovery circuitry may have automatic mode switching capabilities. When operated in reference mode, the clock and data recovery circuit may use a first phase-locked loop to lock onto a reference clock. When operated in data mode, the clock and data recovery circuit may use a second phase-locked loop to lock onto the phase of the differential data stream. A control circuit may automatically switch the clock and data recovery circuit between the reference mode and the data mode. Override signals may be used to force the clock and data recovery circuit out of the automatic mode and into either the reference or data mode.

Abstract: A method and system for booting a microprocessor controlled device. A microprocessor that is designed to read from a linear storage device executes code from a non linear storage device through an interface or emulator that writes and retrieves specially formatted boot instructions to/from the non linear storage device.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to present device information in response to one or more externally generated signals. The second circuit may be configured to store the device information. The third circuit may have (i) a first mode configured to program the device information into the second circuit and (ii) a second mode configured to transfer the device information from the second circuit to the first circuit.

Abstract: An image processing apparatus including an image processing circuit, a frequency dispersion circuit, and a timing signal generator. The image processing circuit processes an image signal, and the frequency dispersion circuit performs frequency dispersion relative to a reference clock signal by continuously modulating an oscillating frequency of the reference clock signal in a predetermined modulation cycle and to generate a frequency dispersion clock signal. The timing signal generator generates a timing signal that controls an operation of the image processing circuit using the frequency dispersion clock signal, in synchronism with the predetermined modulation cycle used for the frequency dispersion.

Abstract: There is disclosed, for use in an integrated circuit, an apparatus for driving a signal line in the integrated circuit. The apparatus comprises: 1) a line driver for receiving an incoming data signal and transmitting an outgoing data signal on the signal line; 2) a power source for supplying a plurality of power voltage levels to a power supply rail of the line driver; and 3) a power level controller for determining a data rate of the outgoing data signal and in response to the determination, selectively applying one of the plurality of power voltage levels to the power supply rail of the line driver to thereby modify an amplitude of the outgoing data signal.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: A memory device (20) having substantially reduced leakage current in a sleep/data retention mode whereby at least a portion (25, 28) of the periphery circuitry (24) shares the same power supplies VDDA and/or VSSA of the memory array (22) such that during sleep/data retention mode the voltage across both the portion (25, 28) of the periphery circuitry (24) and the memory array (22) of the selected SRAM block is reduced, while all other circuits can be shut down except the sleep control circuits as well as selected latches, flip-flops, etc. whose contents need to be retained. A sequence for powering up and shutting down portions of the periphery circuitry (24) and the external circuitry (26) is also provided.

Abstract: A system for power-saving task processing includes a remaining power detector detecting a remaining power of a battery, and a motion information table defining a relationship between the remaining power of the battery on execution of a task and a plurality of processes for each task. Each of the plurality of processes corresponds to a different remaining power of the battery. The system also includes a task controller that chooses and executes one of the plurality of processes from the motion information table according to the detection result of the remaining power detector.