Abstract: The method of the invention is based on an optimum combination of multi-carrier modulation with the spread-spectrum technique. The data of a subscriber station are spread, with the data of a subscriber station being modulated on a set of orthogonal spread sequences and superimposed. The data of a subscriber station are transmitted to a partial quantity of subcarriers in the frequency band, with the partial quantity of sub-carriers associated with the individual subscriber stations being disjunct and distributed over the entire transmission band. A channel estimation required for receiving-side data detection is performed by means of filtering in the time and/or frequency direction of reference symbols. A low-complexity maximum-likelihood sequence estimation is possible for data detection. The method of the invention is well-suited for use for both the upstream and downlinks in future cellular mobile-radio systems.

Abstract: A transmitter for generating and transmitting frequency shift keying signals. The transmitter comprises a resonant circuit, a capacitor, a switch for coupling and decoupling the capacitor to the resonant circuit, a sensor and a controller. The controller includes an input for receiving a data signal. The controller actuates the switch to selectively couple the capacitor to the resonant circuit based on the state of the data signal. The sensor determines when the energy level in the capacitor is substantially zero and the controller synchronizes actuation of the switch with the substantially zero energy state of the capacitor. The transmitter also includes a circuit for efficiently supplying power to the resonant circuit in form the power pulses.

Abstract: A cellular communication signal receiver receives a desired signal in the presence of at least one co-channel interference signal. The receiver comprises a channel estimator configured to receive a plurality of training signal samples to estimate the finite impulse response to the desired signal and the co-channel interference signal. The finite impulse response estimates having a predetermined number of channel taps defining the length of the desired channel and the length of co-channel interference channel. A Viterbi decoder is coupled to the channel estimator, and configured to receive the desired and co-channel interference signals. The channel estimator generates channel tap estimates. A power calculator is coupled to the channel estimator and configured to estimate the power of the estimated channel taps.

Abstract: A clock receiver system (10) includes a clock receiver circuit (14), a phase-lock loop circuit (15), and a clock receiver mirror circuit (16). The clock receiver circuit (14) comprises a differential amplifier having complementary first and second clock inputs and producing a clock receiver output (20). The clock receiver output (20) is applied as a first input to the phase-lock loop circuit (15). The output of the phase-lock loop circuit comprises a phase-locked clock output (22) which is directed to a clock distribution arrangement (25). The signal at the clock distribution arrangement (25) is fed back to the second input of the phase-lock loop circuit (15) through the clock receiver mirror circuit (16). The clock receiver circuit (14) and clock receiver mirror circuit (16) are both self-biased and include identical circuit components.

Abstract: A method and apparatus for disseminating filters from an intermediate network entity called an Administrative Control Point (ACP). The ACP sends dynamic filtering information to various ones of the receiving entities in a network. Thus, receivers in the network can have a set of dynamic filters that can differ from all other sets of dynamic filters in the other receivers. When a receiver receives multicast data, it filters the received data using the filters that it received from the ACP before it processes the received data. The ACP can also update and/or change the filters in one or more receivers at a later time. Dynamic filters can be, for example, software modules, software classes, and/or configuration parameters.

Abstract: The present invention provides a spread spectrum radio transmission digital mobile communication device having RAKE receiving functions and capable of decreasing influence of a delay wave having a delay time smaller than chip time width of a diffusion signal.

Abstract: The invention relates to a digital transmission system comprising a receiver, in which system a trellis-based estimation method (3) with a number of states reduced as a result of feedback (5) of at least one feedback value (.xi.) forms estimates (a) for a received signal (r) by means of an estimated impulse response (h) of a transmission system (1), a feedback value (.xi.) being determined from at least one estimate (a). With reduced-state estimation methods for the digital transmission, the problem consists of the additional noise components caused by the feedback of preliminary false symbol decisions. To achieve optimum estimates (a) for the received signal (r) despite a reduced number of states due to feedback, the receiver forms the feedback value (.xi.) from at least one intermediate value (a.sub.SDF). In digital transmission systems, the transmit symbols (a) and the estimates (a) have the values -1 or 1 in the receiver. In the receiver according to the invention, intermediate values (a.sub.

Abstract: This device includes a main signal path in which a capacitor is included upstream of an analog/digital converter in which a conversion is triggered by a clock. According to the invention, the output of the analog/digital converter is connected to inputs of several threshold detectors which have positive detection thresholds in a progression proportional to consecutive powers of two, and several other threshold detectors which have negative detection thresholds which also progress proportionally to consecutive powers of two, which threshold detectors control current generators whose currents are added together into the capacitor.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: A GPS receiver having a fast time to lock to a GPS signal by storing a time period of an incoming GPS signal in a signal memory and rapidly comparing the signal memory against locations in a replica memory having stored GPS signal replicas. The GPS receiver includes a memory-based search engine for acquiring the GPS signal so that it may be tracked. The memory-based search engine includes a signal memory for storing a millisecond of a digitized GPS signal, a replica memory section for storing replicas representative of the digitized GPS signal for all possible frequency differences between the GPS carrier frequency and a local reference frequency and phase offsets between the GPS code phase and a local reference time, and a GPS memory comparator for comparing the stored signal in signal memory to the stored replicas in replica memory and issuing an acquisition detection signal when the level of the comparison is greater than a selected threshold.

Abstract: A method and system which combines a properly designed FEC and the periodic transmission of known symbols to obtain a desired error performance in a point-to-multipoint digital transmission system employing a DFE which induces error propagation. A transmitter unit includes a forward error correction encoder (FEC) which implements a code to information provided to an input of a data interleaver having block length N and interleaving depth D, and a data modulator which is coupled to an output of the data interleaver to receive a stream of data symbols. At least one receiver unit includes a decision feedback equalizer (DFE) which includes a feedback filter and provides an input to a data deinterleaver having block length N and interleaving depth D, and a FEC decoder which receives data from an output of the data deinterleaver. Sequences of known symbols of length at least equal to the length of the feedback filter are periodically added to the output of the data interleaver.

Abstract: An interface circuit for transmitting binary signals includes a signal transmitting device, a signal receiving device and a transmission device connected therebetween. The signal transmitting device has a device for limiting steepness of ascending and descending edges of the binary signals to certain inclination values which are identical to one another.

Abstract: A method and apparatus for equalizing a received quadrature amplitude modulated signal is disclosed. To equalize the signal, a band edge equalizer (BEE) is used in combination with a symbol spaced equalizer (SSE) and possibly a decision feedback equalizer (DFE). The equalizer's are used along a series path to equalize the QAM signal in a series of equalization operations. By separating the equalization of the signal to separate equalizers, the cost of the equalization can be reduced without substantially affecting performance. In particular, band edge equalizing the QAM signal and symbol space equalizing the symbol can reduce the number of multiplies per second required by any particular equalizer. Accordingly, the equalizers used can be less expensive. Also, using a decimating circuit between the BEE and the SSE that decimates the sample rate of the signal being provided to the SSE can further reduce the number of multiplies per second that must be performed by the SSE.

Abstract: A phase-locked loop which is characterized by using two identical phase shifters and programmable UP/DN counters to generate a timing clock having accurate frequency. The clock which is used to recover the received data is made synchronous with the data by adjusting its phase without affecting its frequency. Therefore, frequency drift caused by data jitter of received data does not occur in the phase-locked loop according to the present invention. Besides, since the invention is an all-digital circuit, it is not sensitive to temperature change, voltage variation, or fabricating process fluctuation. Furthermore, it has excellent noise immunity.

Abstract: An apparatus and method for receiving time skewed data from a parallel data bus. A data transfer on the parallel data bus is preceded by a start-of-cell delimiter consisting of a predetermined sequence of pulses on each of the data signals. The data is received from the bus by receive logic employing a local clock. Sampling logic is used to sample each of the data signals received from the bus at a rate which is higher than the local clock rate. Sample registers store a plurality of samples of corresponding data signals, the number of samples stored being large enough to store at least some of the pulses constituting the start-of-cell delimiter. Start-of-cell detect and center select logic is used for determining that a start-of-cell delimiter is stored in each of the sample registers, and for determining which of the samples stored in each of the sample registers represents the approximate center sample of one of the pulses of the start-of-cell delimiter.