Patents Examined by Thomas G. Bilodeou
  • Patent number: 5792703
    Abstract: A method of making electrical contacts to device regions in a substrate is taught. A first set of contacts are self-aligning and borderless and a second set of contacts are bordered. The method comprises the steps of providing a first insulating layer over the substrate and forming the first set of contacts in a self-aligned and borderless manner. This is followed by forming a second insulating layer over said first insulating layer, in which the second set of contacts that are bordered to the gate electrode and peripheral diffusions are formed through the first and second insulating layers. In addition, bordered contacts to the first set of borderless contacts are formed through the second insulating layer.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: August 11, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gary B. Bronner, Jeffrey P. Gambino
  • Patent number: 5585304
    Abstract: A semiconductor wafer is comprised of a transparent layer interposed between a thin silicon layer and a thick silicon layer. Silicon islands are formed from the thin silicon layer on the transparent layer. Device elements are formed in the silicon islands. Thereafter, the thick silicon layer which is a support layer is etched away to form a transparent region on the wafer. The wafer is constructed to avoid elimination or destruction of the transparent layer during the course of formation of the silicon islands and during the course of etching of the rear thick silicon plate. The transparent layer is comprised of a silicon nitride film or a silicon carbide film. Alternatively, the transparent layer is comprised of a silicon oxide film covered by a silicon nitride film or a silicon carbide film on one or both of the upper and lower faces of the silicon oxide film.
    Type: Grant
    Filed: August 2, 1994
    Date of Patent: December 17, 1996
    Assignees: Agency Industrial Science, Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Kunihiro Takahashi, Hiroaki Takasu, Yoshikazu Kojima, Hitoshi Niwa, Nobuyoshi Matsuyama, Yomoyuki Yoshino, Masaaki Kamiya
  • Patent number: 5580821
    Abstract: A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer o
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: December 3, 1996
    Assignee: Micron Technology, Inc.
    Inventors: Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan