Abstract: A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.

Abstract: Disclosed is an information processing apparatus which includes a processor, one or more input/output devices and an input/output bus for connecting the processor to the input/output devices. A bus connector is included for expanding the input/output bus to an external device. A first switch is used for electrically disconnecting bus signals that are carried by the input/output bus to corresponding connector pins of the bus connector. A second switch is used for electrically grounding the connector pins in the bus connector. The apparatus further includes switch control means for controlling the first and the second switches. When no external device is connected to the bus connector and the connector pins are exposed externally, the first switch is opened to cut off bus signals and to prevent the transmission of high frequency signals to the connector pins.

Abstract: A method and system for uniquely identifying indicia of traits of a participant in an event adapted for use in a boxing match. A plurality of predetermined characteristic corresponding to the traits of a participant to be identified is assigned. Each predetermined characteristic has a predefined format. The assigned characteristic is stored and displayed in a plurality of predefined display format allowing for identification of traits so as to facilitate interpretation and prediction of trends.

Abstract: A highly secure, virus resistant, tamper resistant, object oriented, data processing system for depositing, withdrawing and communicating electronic data between one or more individual and/or networked computers comprising one or more computers for processing electronic data including one or more shared electronic storage devices for the temporary and/or permanent storage of said electronic data, each of said computers including custom configurable system programs for asynchronous depositing, withdrawing and communicating said electronic data to commonly shared electronic storage devices, and said programs permitting data archival, accountability, security, encryption and decryption, compression and decompression, and multi-processing capabilities.

Abstract: In a system that executes the method according to the invention, each slot on the system bus is individually enabled at start-up and each address of an address range is read to determine whether an expansion board is installed in the slot and is responding to a read from that I/O address. If the data value returned by the I/O read is not equal to the undriven value of the data bus, then it is known that the expansion board is responding to that I/O address. Otherwise, a second read of the I/O address is performed, and the values of certain control lines on the system bus are latched to determine whether an expansion board is driving those lines in response to the I/O read. If so, again it is known that an expansion board is responding to a read from that I/O address. Otherwise, the system then performs a further special I/O read to determine the data bus response time.

Abstract: A network provides the capability for information transfer and resource sharing between a plurality of nodes including computers and peripheral devices. The network is comprised of a plurality of network interfaces coupled together on a network cable in both a daisy chain configuration and a bus configuration. Each node is connected to one of the network interfaces using an interface compatible with each particular node. Each network interface contains logic means for controlling the operation of the network. A means for self-identifying the network address of each node is provided without the need for unique hardware or software in each network interface. One of the network interfaces in the network is self-designated as the network watch dog. The network watch dog performs network error detection and correction. The network provides the capability for nodes to communicate with each other even though their associated interfaces are incompatible.