Abstract: An apparatus controls a high-power drive device external to a package of a gate driver circuit. A first circuit charges the control node over a first length of time in response to a first signal through the first node indicating an absence of a fault condition and a first level of a control signal. A second circuit discharges the control node over a second length of time in response to a second signal through the second node indicating the absence of the fault condition and a second level of a control signal. A third circuit includes a current amplifier and is configured as a soft shutdown path to discharge the control node over a third length of time in response to the first signal through the first node indicating a presence of the fault condition. The third length of time is different from the second length of time.

Abstract: A bandgap reference circuit including a clamp circuit is provided. The bandgap reference circuit performs the calibration only for one time in a normal mode to store a control code of a reference generator of the clamp circuit. In a suspend mode, the control code is used for controlling the reference generator to cause the clamp circuit to provide a desired source voltage, and a bandgap reference voltage source is shut down to reduce the power consumption.

Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.

Abstract: A power supply system for a vehicle, the system including: a battery pack including at least two parallel strings of battery cells, each string forming a battery having a first output voltage; a switch mechanism configured to connect one of the at least two batteries to a first battery pack output terminal, wherein the first battery pack output terminal is connected to a first power consumer; and a multichannel DC/DC converter having an input terminal connected to the first battery pack output terminal, the multichannel DC/DC converter including a plurality of outputs, wherein at least one of the plurality of outputs is configured to provide a second voltage, the second voltage being lower than the first voltage, and wherein the at least one output of the multichannel DC/DC converter is connected to a second power consumer.

Abstract: A system, method and apparatus for providing pulsed power comprises a trigger comprising a pulse generator and a photonic transmitter and a multi-stage switch comprising a gate driver circuit, the gate driver circuit further comprising a plurality of transistors connected in series and a plurality of driver stages wherein each of the transistors is turned on and off simultaneously by the plurality of driver stages.

Abstract: According to a synchronization method, a basic timing signal generation circuit generates a basic timing signal. A communication control circuit generates a first communication cycle timing signal, measures an input difference between the basic timing signal and a predetermined one of first communication cycle timing signals, divides a compensation value responsive to the input difference by the number of first communication cycle timing signals, adds up a value resulting from the division in a communication cycle, compensates for timing of generating the first communication cycle timing signal with timing equal to or greater than a predetermined value, and transmits timing compensation data to external equipment. The external equipment generates a second communication cycle timing signal, compensates for timing of generating the second communication cycle timing signal based on timing of receipt of the timing compensation data, and synchronizes with the first communication cycle timing signal.

Abstract: A powered device (PD) used for power over Ethernet (PoE), where the PD includes an Ethernet port and a rectifier circuit. The rectifier circuit includes a first control circuit and a second control circuit, where the first control circuit is configured to control a first metal-oxide semiconductor field-effect transistor (MOSFET) and a second MOSFET, avoid turning on the first MOSFET and the second MOSFET at a PoE detection stage, and turn on at least one of the first MOSFET or the second MOSFET at a PoE power supply stage. The second control circuit is configured to control a third MOSFET and a fourth MOSFET, turn on at least one of the third MOSFET or the fourth MOSFET at the PoE power supply stage, and avoid turning on the third MOSFET and the fourth MOSFET at the PoE detection stage.

Abstract: A device with a noise shaping function in sampling frequency control includes a first adder, an N-bit quantizer, a mapping circuit, a second adder, a first D flip-flop, a scaler, and a second D flip-flop. The first adder generates a first value according to an input signal, a second value, and a third value. The N-bit quantizer outputs a codeword to a controller according to the first value. Frequency adjusting orders corresponding to codewords outputted by the N-bit quantizer are between a smallest predetermined negative value and a largest positive predetermined value, the controller utilizes an adjusting order corresponding to the codeword to make a frequency generator generate adjusted sampling frequency, and N is an integer greater than 2. The first D flip-flop, the scaler, and the second D flip-flop are used for providing a high-pass filter effect to the device.

Abstract: A high-voltage level shifter circuit that is capable of level shifting a signal from a low-voltage rail to a high-voltage rail for effective gate driving of a top power switch, with a short propagation delay and a high common-mode transient immunity (CMTI). The high CMTI high-voltage level shifter circuit can include a differential input and isolation stage, a high dv/dt sensor and cancellation stage, at least one differential and common-mode gain stage, and an output buffer stage.

Abstract: Effectively utilize a capacitor for supplying power to a load when a battery abnormality occurs. A power supply device for connecting to a battery and a load to which power is supplied from the battery includes: a capacitor; a first switch for switching a connection state between the battery and the capacitor; a second switch for switching a connection state between the capacitor and the load; and a control unit for detecting a state of charge of the capacitor and abnormality of the battery. When the abnormality of the battery is not detected, the control unit turns on the first switch and turns off the second switch when the capacitor is not charged, and maintains the first switch on after the capacitor is fully charged.

Abstract: A charge pump circuit has a plurality of charge pump stages cascaded to one another between an input terminal and an output terminal to provide an output voltage having a boosted value with respect to the input voltage. A clock generator is configured to generate a clock signal provided to the charge pump stages to perform the boosting of the input voltage. An output-voltage regulation feedback closed-loop is coupled to the clock generator to perform a regulation of the output voltage based on a feedback voltage. A discharge control stage is configured to control a discharge of the charge pump circuit by generating a first discharge control signal configured to disable the output-voltage regulation feedback closed-loop or a second discharge control signal configured to reduce the frequency of the clock signal.

Abstract: A data interface is disclosed, which includes an electrostatic discharge circuit, and a charge transmitting circuit connected to a binding wire through the electrostatic discharge circuit; the charge transmitting circuit includes a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire. According to the data interface, charges in a charging capacitor and a parasitic capacitor are redistributed, which could not only reduce a power consumption loss caused by a parasitic capacitor in a communication channel but also effectively reduce time delay. In addition, the use of dual-wire communication is avoided by using single-wire communication, and the manufacturing costs are reduced relative to low-voltage differential signaling (LVDS).

Abstract: The present invention provides a clock data recovery apparatus and an operation method thereof. The clock data recovery apparatus includes an equalizer, a phase detector, a charge pump, and an oscillation circuit. The equalizer is configured to equalize raw data to generate equalized data. The phase detector is coupled to the equalizer to receive the equalized data. The phase detector is configured to generate a detection result according to the equalized data. The phase detector performs pattern-filtering on the equalized data to filter out at least one pattern. The charge pump is coupled to the phase detector to receive the detection result. The charge pump is configured to generate a control signal according to the detection result. The oscillation circuit is coupled to the charge pump to receive the control signal. The oscillation circuit is configured to generate a clock signal according to the control signal.

Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Abstract: A method is provided for power limiting in a power inverter configured to produce an output voltage and having a voltage regulator with a voltage setpoint defined for no load on an external bus line. The method includes determining a power level related to a load on the external bus line, determining an adjusted voltage setpoint based on the power level, including: decreasing the voltage setpoint to the adjusted voltage setpoint having a first value when the power level is above a maximum threshold, increasing the voltage setpoint to the adjusted voltage setpoint having a second value when the power level is below a minimum threshold, and slewing the adjusted voltage setpoint to the voltage setpoint so that the adjusted voltage setpoint has a third value when the power level is within a range defined by the maximum threshold and the minimum threshold.

Abstract: The present invention concerns a method for controlling the temperature of a multi-die power module, comprising: determining and memorizing a first weighted arithmetic mean of junction temperatures of the dies of the multi-die power module, determining successively another weighted arithmetic mean of junction temperatures of the dies, checking if the difference between the other weighted arithmetic mean and the memorized weighted arithmetic mean is lower than a first predetermined value, enabling a modification of the duty cycle of an input signal to apply to at least one selected die of the multi-die power module if the difference is lower than a first predetermined value, disabling a modification of the duty cycle of the input signal to apply to the at least one die of the multi-die power module if the difference is not lower than the first predetermined value.

Abstract: System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.

Abstract: According to one or more embodiments of the present invention, a delay circuit includes a first sub-circuit that delays a leading edge of an input signal according to first control settings, the input signal being for an electric device. The delay circuit further includes a second sub-circuit that delays a trailing edge of the input signal according to second control settings. An output signal from the delay circuit is received by the electric device.