Abstract: A method for writing tagged (partitioned and classified) records from a first log stream to multiple recovery streams and discarding same from said first stream at the termination of the unit of recovery in a transaction-oriented system to permit first log stream reuse.
June 30, 1986
Date of Patent:
October 31, 1989
International Business Machines Corporation
Kenneth M. Kapulka, Holly A. Rader, Jimmy P. Strickland
Abstract: An improved mixed object editor flows text around and into irregularly shaped graphic objects on a page so that all the "white" space on the page is filled. An irregularly shaped window which generally conforms to the shape of the graphic object is first created. Then the boundaries of text lines which intersect the irregularly shaped window are determined. Text is next placed in the available text space.
Abstract: A system bus control circuit associated with a central processing unit that generates control signals and in which the control circuit is constructed of a timing circuit having a plurality of successively connected timing stages constructed of data flip-flops for respectively generating sequentially time-displaced timing control signals. A gate array is employed for providing additional logic gating. The control signal from the central processing unit coupled to one group of input lines of the gate array. A second group of input lines to the gate array are coupled from the timing circuit and in particular the individual stages of the timing circuit. The output lines from the gate array generate timing signals that control data bus operation.
Abstract: Disclosed is a computer system (FIG. 1) that is operable with any multiplexed-address memory (200) within a size range of 2.sup.N to 2.sup.N+R memory locations (211). The system has a memory of 2.sup.S locations selected from the predetermined range, and the memory has S/2 multiplexed address input terminals (231). Address bits forming a memory address, generated for example by a processor (400), are multiplexed by a memory controller (300) onto N/2+R address output terminals (314) in two sets of N/2+R address bits. The address bit sets have at least R/2 bits in common. An address bus (250) transports the multiplexed address bits to the memory. The bus has N/2+R address leads (251) connected to the output terminals of the memory controller. S/2 of those address leads are also connected to the address input terminal of the memory. The remaining address leads are not connected. The memory controller multiplexes the address of any memory within the predetermined range onto its output terminals.
August 8, 1983
Date of Patent:
June 23, 1987
American Telephone and Telegraph Company AT&T Bell Laboratories
Abstract: A bus interface device for a data processing system in which 2M units are interconnected and exchange information bits over a bus comprising at least M lines.The device comprises a receiving circuit associated with each respective line (D0-D7) of the bus and including two flip-flops 40 and 41 that assume the voltage level on the input line at the up-going and down-going transitions of a clock signal (CLK1) and are restored at the down-going and up-going transitions of that signal. When the bits received over the bus are encoded in the NRZ code, using a bit period equal to half a period of the clock signal, OR circuit 47 provides at its output the resynchronized train of input bits received over D0-D7.The 2M units are divided into two groups, with the units in each group requesting access to the bus during either phase of a second clock signal (CLK2). When the bus is free, flip-flops 48 and 49 provide an indication of the requests for access to the bus made by the associated units.