Abstract: A regulator converting an input voltage into a supply voltage includes a first differential amplifier, a second differential amplifier, a pass element, and a feedback voltage divider. The first differential amplifier includes a reference voltage with a feedback voltage to generate a first output voltage and a first inverse output voltage. The second differential amplifier compares the first output voltage and the first inverse output voltage to generate a second output voltage. The pass element passes an output current from the input voltage to the supply voltage according to the second output voltage. The feedback voltage divider divides the supply voltage by a feedback factor to generate the feedback voltage.

Abstract: An apparatus includes an integrated circuit (IC). The IC includes a current source, to sink or source an output current, in response to a control signal, and a switch-capacitor resistor coupled to the current source. The apparatus further includes a controller coupled to derive the control signal from a voltage across the switch-capacitor resistor, the controller further to provide a switch control signal to the switch-capacitor resistor.

Abstract: A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock.

Abstract: In accordance with an embodiment of the present invention, a method of controlling current through a transistor includes measuring a voltage across the transistor, measuring a current through the transistor, determining a safe operating current for the measured voltage across the transistor, and adjusting a voltage of a control node of the transistor using a feedback controller until the measured current through the transistor is not greater than the determined safe operating current.

Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

Abstract: Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.

Abstract: A regulated charge pump circuit and method of operation are described. A charge pump is configured to supply an output voltage to a load, and includes at least one charge pump stage, a charge pump driver arranged to drive the charge pump stages and a controllable current source connected between a supply voltage and the charge pump driver. An analog regulation loop includes a measurement circuit arranged to output an analog regulation signal indicative of a difference between a current value of the output voltage and a target value of the output voltage. A signal path is connected to the charge pump to supply the analog regulation signal to the controllable current source to operate the controllable current source to modulate the supply voltage that can be provided to the charge pump driver to regulate the output voltage.

Abstract: A system for high powered wireless power delivery and charging includes an electronic device having a wireless charging module. The wireless charging module includes a power management module, the power management module configured and executing instructions to enable and disable the power delivery or charging of the electronic device based on whether a valid charging circuit exists, the power management module additionally configured and executing instructions to prevent a detection of an invalid load.

Abstract: There is provided a circulator device. The circulator device comprises two magnet-free circulators. Each magnet-free circulator has a forced time variance. The circulator device comprises ports. The two circulators are in the circulator device arranged to have mutually anti-phase time variance. Each of the two circulators is coupled to all of the ports. There is also presented an isolator device comprising such a circulator device. There is also presented a radio transceiver device comprising such a circulator device or isolator device.

Abstract: An output driver includes a switching device having a first node coupled to a gate of a power switch and pulling down a voltage level of the gate of the power switch to prevent a premature turn-on of the power switch. A pull-down circuit is coupled to the switching device and keeping the switching device from being turned on to prevent the premature turn-on of the power switch.

Abstract: According to examples, an apparatus may include a field effect transistor (FET), a driver to receive an input signal and to output a driver output signal, and a gate to receive the input signal. The apparatus may also include a delay element to receive the driver output signal and to output a delayed signal to the gate after a delay from receipt of the driver output signal, in which the gate is to output a gate output signal to the FET in response to receipt of the input signal and the delayed signal, and in which receipt of the gate output signal by the FET drives the FET to provide a boost to the driver output signal.

Abstract: A DC switching device has at least one switching unit which is arranged between two terminals. Further, the DC switching device has a control unit for controlling the at least one switching unit. The switching unit has a first and a second semiconductor switching element, which are arranged in parallel with one another, the first switching element being a high-voltage switching element and the second switching element being a low-power-loss switching element. The switching unit is controllable by the control unit in such a way that, when the switching unit is switched off, initially the second switching element is switched to be non-conductive, and subsequently the first switching unit is switched to be non-conductive, and when the switching unit is switched on, initially the first switching element is switched to be conductive and subsequently the second switching element is switched to be conductive.

Abstract: In an example, an input buffer includes: first buffer circuit having an output, a first voltage control node, and a second voltage control node; a first transistor having a gate coupled to the output of the first buffer circuit, a drain, and a source; a second buffer circuit having an input coupled to a reference voltage and an output coupled to the source of the first transistor; and a first current source having a reference output coupled to the drain of the first transistor, a first output coupled to the first voltage control node of the first buffer circuit, and a second output coupled to the second voltage control node of the second buffer circuit.

Abstract: A level shifter (100) is presented comprising an input branch (102) and an output branch (104). The input branch comprises a first switch (130), a voltage clamping unit (120) and a controllable current source (110) in series. The output branch (104) comprises a second switch (140) and a third switch (150) in series, the second switch (140) and third switch (150) having opposite polarities. An output (OUT, 160) is provided between the second and the third switch (140, 150). The current source (110) is controlled by an input signal (IN) and the output signal (OUT). The first switch (130) is controlled by the input signal (IN). Switching control terminals (122, 124) of the second and the third switch are connected on either side of the clamping unit (120). This reduces voltage swing of switching control units, thus resulting in fast switching, less power consumption and wider voltage ranges.

Abstract: To provide a driving device for semiconductor elements that is capable of suppressing variation in switching time caused by driving capability and temperature. A driving device for semiconductor elements includes: a semiconductor chip in which a voltage control type semiconductor element is formed; a temperature detecting unit configured to detect temperature of the semiconductor chip; a driving-capability adjusting unit configured to adjust driving capability of the voltage control type semiconductor element according to temperature detection values detected by the temperature detecting unit; and a timing adjusting unit configured to adjust switching time of the voltage control type semiconductor element according to the temperature detection values detected by the temperature detecting unit.

Abstract: A delay-locked loop circuit and a selection method of unit coarse delay are provided. The delay-locked loop circuit includes a frequency detector and a unit coarse delay selector. The frequency detector receives a reset signal and a clock signal. The frequency detector performs a sampling operation to detect a clock frequency of the clock signal based on a time shift of the reset signal and a sequential delay of the reset signal to generate a plurality of determining signals. The unit coarse delay selector selects one of the plurality of determining signals with an earliest transition time as a selected coarse delay signal to control a timing of the delay-locked loop circuit.

Abstract: An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

Abstract: An RF switch includes series-coupled RF switch cells coupled between an RF input and ground, a transistor including a first current node coupled to a first load resistor, a second current node coupled to ground, and a control node coupled to an internal switch node, and a filter having an input coupled to the first current node of the first transistor and an output for providing a DC voltage corresponding to the RF power present at the internal switch node.

Abstract: A gate driver circuit for driving a high-side switch is disclosed. The gate driver circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The gate driver circuit further comprises a sampling capacitor. The sampling capacitor is configured to sample an output voltage of an at least one amplifier. The gate driver circuit additionally includes at least one voltage supply. The at least one voltage supply is connected to the at least one amplifier. The sampling capacitor is configured to charge a gate capacitance of the high-side switch, and the at least one amplifier is configured to limit a high-side switch output current.

Abstract: The invention addresses providing a semiconductor device that enables to reduce noise simultaneous with switching. A driver IC which is a semiconductor device includes a drive circuit which drives a control terminal of a PMOS drive stage which is a switching element, a noise detection circuit which detects noise in an output signal when switching (turning) the PMOS drive stage on or off, and a control circuit which control driving by the drive circuit based on the detected noise.