Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

Abstract: An extensible filter structure is disclosed allowing realizable effective filtering over many decades in frequency. Multiple devices operating with mismatched frequency ranges can be multiplexed together with or without switching.

Abstract: Disclosed are various embodiments for distributing power to loads and classifying loads that receive electrical energy in the form of guided surface waves that are transmitted by guided surface waveguide probes along a terrestrial medium.

Abstract: Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).

Abstract: In order to control a plurality of inverters, which are connected on their input side to a current source each and on their output side to a common grid connection point, electrical variables are measured at the individual inverters and are used for controlling the individual inverters, currents being output by the individual inverters depending on the electrical variables measured at the location of the individual inverters Effects of the connection equipment between the individual inverters and the common grid connection point on currents are determined, electrical variables being measured at the grid connection point and are set in relation to the electrical variables measured at the same time at the individual inverters. The connection equipment between the individual inverters and the common grid connection point is taken into consideration in controlling the individual inverters.

Abstract: A transmission circuit includes: a first transistor, a first current source, a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type.

Abstract: Disclosed are various embodiments for transmitting energy conveyed in the form of a guided surface-waveguide mode along a lossy conducting medium such as, e.g., the surface of a terrestrial medium by exciting a polyphase waveguide probe. A probe control system can be used to adjust the polyphase waveguide probe based at least in part upon characteristics of the lossy conducting medium.

Abstract: A wireless power transfer system including a plurality of power supply coils, and wirelessly performing power transfer from the power supply coils to a power receiver, includes an entire controller. The entire controller is configured to control the power transfer performed by wirelessly transmitting and receiving powers of the power supply coils and the power receiver, in accordance with confirming power transfer ranges of the plurality of power supply coils.

Abstract: Provided is a power receiving device in which supply of power from a power supply device can be stopped while a reduction in Q-value is suppressed. The power receiving device includes a first antenna which forms resonant coupling with an antenna of the power supply device; a second antenna which forms electromagnetic induction coupling with the first antenna; a rectifier circuit including a plurality of switches and performing a first operation or a second operation depending on whether the plurality of switches is ON or OFF, the first operation being an operation in which voltage applied from the second antenna is rectified to be outputted, and the second operation being an operation in which a pair of power supply points is short-circuited; a load to which the voltage is applied; and a control circuit which generates a signal for selecting ON or OFF of the plurality of switches.

Abstract: A power distribution system including first and second ac busbars connected to ac generators. A first active rectifier/inverter has ac input terminals electrically connected to the first ac busbar. A second active rectifier/inverter has ac input terminals electrically connected to the second ac busbar. A first dc interface is electrically connected to dc output terminals of the first active rectifier/inverter and a second dc interface is electrically connected to dc output terminals of the second active rectifier/inverter. The dc interfaces include reverse blocking means. A third active rectifier/inverter operates as a drive and has dc input terminals electrically connected in the parallel to dc output terminals of the first and second dc interfaces by means of an interposing dc busbar. An electric motor, that can optionally form part of a marine thruster T1, is electrically connected to ac output terminals of the third active rectifier/inverter.

Abstract: Self-discharging reserve power units and related methods are described. A self-discharging reserve power unit comprises an electrical energy storage component to provide power to a process control device. The electric energy storage component is coupled to an energy discharge component and a controller, which causes the discharge component to discharge energy from the electrical energy storage component following completion of an operation by the process control device.

Abstract: A power control apparatus, a vehicle having the same, and a method of controlling the vehicle are provided. The power control apparatus includes a communication unit that is configured to receive a request message related to a power setting via a communication network in a vehicle and a determination unit that is configured to determine a power condition based on the request message related to the power setting. Additionally, an application controller is configured to execute an application of power supplied from at least one among a battery and an alternator power supply based on a result of the determination.

Abstract: The present invention relates to an insulated gate bipolar transistor (IGBT) driver module for driving at least one gate of at least one IGBT device, and method therefor. The IGBT driver module comprises at least one series capacitance operably coupled between a driver component of the IGBT driver module and the at least one gate of the at least one IGBT device. The IGBT driver module further comprises at least one series capacitance charge adjustment component controllable to determine a gate voltage error (?Gerr) at the at least one gate of the at least one IGBT device and dynamically adjust a charge of the at least one series capacitance based at least partly on the determined gate voltage error (?Gerr).

Abstract: A DC-to-DC voltage converter comprising a differential charge pump that utilizes a differential clocking scheme to reduce output electrical noise by partial cancellation of charge pump glitches (voltage transients), and a corresponding method of operating a differential charge pump. The differential charge pump can be characterized as having at least two charge pump sections that initiate charge pumping in opposite phases of a clock signal to transfer (pump) charge to storage capacitors. The differential charge pump is particularly well suited for implementation in integrated circuit chips requiring negative and/or positive voltages, and multiples of such voltages, based on a single input voltage.

Abstract: The invention relates to a current source for the delivery of a first current and a second current, wherein the first current is biased opposite to the second current. The current source provides a first transistor, wherein the first transistor is connected with a control terminal to a first control voltage. The current source provides a second transistor, wherein the second transistor is connected with a control terminal to a second control voltage. The source terminal of the first transistor is connected in an electrically conducting manner to the source terminal of the second transistor. The first current is delivered at the drain terminal of the first transistor, and the second current is delivered at the drain terminal of the second transistor. Furthermore, a circuit arrangement with a current source according to the invention is provided according to the invention.

Abstract: To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch.

Abstract: A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.

Abstract: A monitoring circuit for a CES element is provided. The circuit includes a control circuit and an output circuit. The control circuit is configured to vary a control signal provided to the CES element. The control signal may be varied for determining an impedance state of the CES element. The output circuit provided an output signal in dependence on the determined impedance state of the CES element.

Abstract: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

Abstract: A controller for use in a power converter includes a comparator to compare a current sense signal with a current limit to generate a comparator output signal representative of whether a switch current has reached the current limit. A drive circuit controls switching of a power switch to regulate an output of the power converter in response to a feedback signal and the comparator output signal. The drive circuit turns off the power switch in response to the comparator output signal. A current limit generator generates an initial current limit in response to the feedback signal. The current limit is responsive to the initial current limit. A light load sense circuit outputs a light load signal in response to sensing a light load condition of the power converter. A modulation circuit outputs a modulation signal and modulates the initial current limit in response to the light load signal.