Patents Examined by Thomas, Tom
  • Patent number: 5141886
    Abstract: An electrically erasable, programmable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.
    Type: Grant
    Filed: February 19, 1991
    Date of Patent: August 25, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Kiyoshi Mori