Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

Abstract: An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the non-volatile fuses. The delay element can include capacitors that are selectively coupled to a propagation path in response to the data stored in the fuse circuits. In one embodiment, data stored in the programmed fuses is copied to volatile latch circuits for use during operation of the timing circuit. The adjustable timing circuit can be provided in any integrated circuit, but is particularly useful in memory devices. The timing system allows for testing and fine-tuning signal processing in the integrated circuits.

Abstract: An instant-on PC is described which can be revived from a sleep state in a matter of seconds. This is carried out by keeping certain power-managed devices in a quickly-revivable state, e.g., the memory and certain elements on the motherboard chipset. Certain PCI devices are also enabled in a quick wake-up state so that they can wake up on a specified stimulus. The power consumption of each of these devices is obtained and it is determined if that power consumption exceeds the power capability of the auxiliary power supply. If not, the more aggressive sleep state is enabled. If so, however, the system takes action to either enter a less aggressive sleep state or to selectively de-enable certain ones of the devices that are in the keep-awake state. Preferably the choice of which to do is made by the user.

Abstract: A method for transmitting data between a microprocessor and an external memory module through external package pins of the microprocessor, which includes the steps of: a) deciding N-bit full sized data to be transferred by using M, wherein N and M are positive integers and N is greater than M; b) sequentially transferring N/M number of M-bit divided data; c) temporarily storing N/M number of M-bit divided data; and d) combining the N/M number of M-bit divided data into the N-bit full sized data.

Abstract: A method and circuit is disclosed for tagging and invalidating speculatively executed instructions. The method includes fetching a first plurality of instructions which includes a conditional branch instruction which identifies a target address if the branch is taken. The conditional branch instruction is detected and in response thereto first and second instruction tags are generated. At least a first instruction is tagged with the first instruction tag wherein the first instruction is included in the first plurality of instructions and wherein the first instruction sequentially follows the first conditional branch instruction in program order. Thereafter, a second plurality of instructions are fetched wherein the second plurality of instructions corresponds to the target address of the conditional branch instruction. At least one of these second plurality of instructions is tagged with the second instruction tag. Thereafter, the conditional branch instruction is executed and resolved.