Abstract: An apparatus and method as shown in for processing digital signals in a communications system including a non-equaliser detector and a equaliser each for receiving an input signal and outputting a quality estimate and bit decision, respectively, so that the quality estimates are compared and a bit decision is made based on the comparison. The apparatus and method further include retraining the equaliser based on the comparison of the quality estimates of the detector and equaliser.

Abstract: A digital filter circuit includes a first input for samples of a digital signal, a subtractor, an adder and a first clocked register connected in series. The first input of the circuit is connected to the minuend input of the subtractor and the output of the first clocked register is connected to the subtrahend input of the subtractor. The second clocked register connected in series at a position between the output of the subtractor and a first input of the adder stores the difference from the subtractor or a value proportional to it. A third clocked register latches the value in the first clocked register and supplies it as a second input to the adder. The filtered output is taken from the first or third register. The circuit optionally includes a scaler connected in series between the output of the subtractor and the first input of the adder. The scaler optionally operates by shifting the digits to positions of less significance.

Abstract: A signal processing system includes a phase locked loop for locking a largest sine wave phase and frequency element of an incoming analog signal; an amplitude estimator for estimating a maximum amplitude of the incoming signal; a multiplier for multiplying the estimated largest sine wave phase and frequency element by the estimated maximum amplitude to provide an estimated largest sine wave component; and a subtractor for subtracting the estimated largest sine wave component from the incoming signal to provide a diagnostic signal.

Abstract: A phase-lock loop (PLL) circuit can be locked on to a synthesizer frequency without decreasing the available range of the frequency differences which the PLL circuit can accommodate during a data receive mode. An analog-to-digital conveyer (ADC) receives an analog input signal and responds to a periodic clock signal by providing a corresponding digital output signal. A phase comparator is coupled to receive the ADC digital output signal and to provide a phase error signal which is representative of a phase error in the digital output signal. A filter accumulates the value of the phase error signal into a filter first register to generate a primary frequency error value. The filter further includes a filter second register for holding a secondary frequency error value (e.g., a value which corrects for an offset between a synthesizer frequency and the PLL free-running frequency).

Abstract: A testing device is provided to test performance of transmission systems such as communication devices and transmission lines by transmitting and receiving specific patterns called pseudo-random patterns (i.e., PN patterns). A receiver unit of the testing device provides a synchronization detecting circuit. The synchronization detecting circuit comprises a pseudo-random-pattern creating circuit, a first coincidence detecting block, a second coincidence detecting block and an OR circuit. The first coincidence detecting block detects coincidence between a receiving-data input, a first detected-pattern input and a pseudo-random pattern created by the pseudo-random-pattern creating circuit so as to produce a first coincidence detecting signal. The second coincidence detecting block detects coincidence between the receiving-data input, a second detected-pattern input and the pseudo-random pattern so as to produce a second coincidence detecting signal.