Abstract: A method and circuit improves the timing of a static column mode device by extending the valid write time to be equal to the write time in a fast page mode device. In particular, the circuit extends the global write enable signal and maintains the address in the address latch to increase the valid write time. Also, the circuit of the present invention improves the noise margin in the static column mode device by decoupling the write enable and column address strobe signals after they are initially received to ignore any noise in those signals. A timer is used.

Abstract: A charge pump has a reference circuitry (18, 20, 22), a first parallel current path (16), at least one second parallel current path (16), a mirror circuit (46), a sourcing circuitry (60, 62) and a sinking circuitry (50, 54, 66, 68). The first and the at least one second parallel current path sink current from a first node responsive to a predetermined voltage generated by the reference circuitry. The at least one second current path also operates responsive to a control signal. The mirror circuit generates a second predetermined voltage responsive to the total current sunk from the first node. The sourcing circuitry and the sinking circuitry sourcing and sinking a current from the output node, respectively, responsive to the second predetermined voltage and to a control signal. The disclosed charge pump may be incorporated into a phase locked loop circuit where constant stability parameters are desired.

Abstract: An isolation linear amplifier circuit provides and utilizes coupling of switched-capacitors. An input differential signal is converted to a proportionated charge on the capacitor by gates controlling of charging and discharging of appropriate capacitors. Then the charge is detected by a differential amplifier with high input resistance. The isolation barrier is established by a configuration of capacitors and an array of gating switches.

Abstract: A delay circuit is provided with an npn type of transistor of which a base is connected to an input terminal, a first constant current source through which a constant current flows from an emitter of the transistor to ground, a first capacitor arranged between the emitter of the transistor and an electric source terminal, a second capacitor C.sub.22 arranged between a collector of the transistor and an output terminal, a first resistor arranged between the emitter of the transistor and the output terminal, a second resistor arranged between the collector of the transistor and the electric source terminal. The constant current of the constant current source is changeable, and an emitter resistance of the transistor is changed depending on the constant current. Therefore, an analog signal applied to the input terminal is changeably delayed by coaction of the resistors, the capacitors and the emitter resistance adjusted by changing the constant current of the constant current source.

Abstract: A sequential amplifier having at least two amplifier stages separated by a delay device such that switching means may energize either or both amplifier stages at any given time to obtain maximum gain of the input signal so long as no oscillations occur between stages, thus allowing a signal to be amplified by adjacent amplifier stages without the adverse effects of feedback associated therewith.

Abstract: Preamplifying circuitry amplifies sound signals for input into a computer system. A first stage common-emitter amplifier provides high-gain amplification of the input signal, while a second stage amplifier comprising an operational amplifier is suitable for driving a cable with the amplified sound signal. A low-cost constant voltage source comprising a diode and an operational amplifier supplies a voltage reference to both amplifier stages with a very high rejection of system noise. The circuitry and methods of the present invention provide a low-cost, easily manufactured preamplifier suitable for sound input in desktop computing devices.

Abstract: In the case of amplifier circuits realised in modern MOS technology, non-linear distortion occurs as a result of the high field strengths in the channel region due to the small dimensions. This distortion is eliminated and noise is reduced in that the amplifier circuit comprises a first series combination of first and second MOS transistors, and a second series combination identical with the first series combination and forming a long tailed pair circuit with the latter. The long tailed pair circuit includes an additional differential amplifier having its output connected to the gate electrode of a load transistor of the long tailed pair circuit by way of a voltage divider. The transistors in the long tailed pair circuit are mutually identical.

Abstract: A modular filter (11) that operates at low voltages and utilizes common mode feedback is described. The modular filter (11) receives an input differential signal and provides a filtered output differential signal. The modular filter (11) comprises a load circuit (15) , a first transconductor (18) , a second transconductor (24) , an amplifier (19), and a common mode amplifier (26). The first transconductor (18) has a transconductance gml and the second transconductor (24) has a transconductance g.sub.m2. The amplifier has a gain K. The modular filter (11) provides a transfer function of V.sub.o /V.sub.i =(g.sub.m1 /g.sub.m2)*((1+(sKC.sub.a /g.sub.m1))/(1+(s (C.sub.a +C.sub.b)/g.sub.m2)), where C.sub.a are capacitors (21 and 22) that capacitively couple outputs of the amplifier (19) to the load circuit (15) and C.sub.b are capacitors (27 and 28) that capacitively couples the output of the common mode amplifier (26) to the load circuit (15).

Abstract: An amplifier for amplifying RF signals comprises a transistor, a first impedance, an impedance transformer, and a tuned resonant circuit. The amplifier receives the RF signals via a signal terminal of the transistor, wherein the RF signals are amplified by the transistor, the tuned circuit, the first impedance, and the impedance transformer. The degree of amplification is based on the impedance ratio between the impedance transformer and the first impedance, wherein the first impedance may be an output impedance matching transformer.