Abstract: A liquid crystal display device includes a display pattern portion including a plurality of transparent electrodes extending mutually in parallel, a terminal portion including a plurality of lead patterns extending mutually in parallel with a pattern pitch narrower than that among the transparent electrodes, and connection patterns for connecting the transparent electrodes and the lead patterns. The connection patterns consist of first connection patterns leading obliquely from the transparent electrodes to extend mutually in parallel and having a common pattern width, and second connection patterns leading straight from the lead patterns to connect with the first connection patterns at a predetermined angle and having a common pattern width.

Abstract: To avoid forward biasing the diodes within an N-channel transistor, the body and source of the N-channel transistor are switchably connected via a high-voltage FET. The gates of the N-channel transistor and high-voltage transistor are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor shorts the body and source of the N-channel transistor. When both transistors are off, the body and source of the N-channel transistor are disconnected and a third transistor couples the body to a reference potential. The N-channel transistor and high voltage transistor share a common body in a semiconductor substrate. The source of the N-channel transistor provides an output terminal for the circuit. A number of these devices, each connected to a different supply voltage, can be connected to the same output terminal and selectively energized to form a voltage multiplexer.

Abstract: A two stage gate drive circuit (10) for controlling a power transistor (12) has been provided. The drive circuit includes a first stage (14) coupled to a first supply voltage terminal for providing a high current drive signal to the power transistor for quickly switching on the power transistor. However, once the power transistor is turned on, the first stage becomes inactive and a second stage (16) coupled to a second supply voltage terminal provides a low current drive signal to the power transistor for fully enhancing the power transistor and lowering its on resistance. The gate drive circuit further includes a timer circuit (18) for rendering the first stage active for predetermined period of time.

Abstract: Two sets of data buses, two equalizing circuits and two amplifying circuits are provided. A selection signal generating circuit generates selection signals for alternately selecting data buses. When the data bus is selected, the equalizing circuit is activated and the amplifying circuit is activated. The data bus is selected, the equalizing circuit is activated and the amplifying circuit is activated.

Abstract: A serial access memory includes a pair of bit lines, a plurality of memory cells each coupled to one of the bit lines and a pair of data lines. The serial access memory also includes a sense amplifier drive line, a sense amplifier, data latch circuit, data transfer circuit and a drive capability control circuit. The sense amplifier drive line is coupled to a potential source for supplying a sense amplifier drive signal from the potential source. The sense amplifier is coupled to the bit lines and the sense amplifier drive line for amplifying a difference of electrical potentials appeared on the bit lines in response to the sense amplifier drive signal. The data latch circuit is coupled to the bit lines and the data lines for latching the amplified electrical potentials appeared on the bit lines as data. The data transfer circuit is coupled between the bit lines and the data latch circuit for controlling an electrical connection between the bit lines and the data latch circuit.

Abstract: The present invention is directed to a voltage controlled single-package integrated circuit device, capable of thermal compensation, for biasing a quasi-linear bipolar device. The bias circuit also provides a low impedance source to a RF device so that the bias point does not dynamically change with the RF signal, thus improving linearity. Changes in the base-emitter voltage level of the RF device are monitored by a reference diode to provide automatic temperature compensation. The reference diode is in close thermal proximity to the RF device, allowing for accurate thermal tracking. The base-emitter voltage may be electronically adjusted by means of a control voltage input, such being suitable for hook-up to a computer system having a digital to analog convertor thereby allowing for fine voltage adjustments. The control voltage may also be used to adjust the class of operation of the RF device or provide external temperature control.

Abstract: A dynamic random access memory device is responsive to a row address signal and a column address signal supplied in synchronism with a system clock signal for providing a data path from a data input/output port and a memory cell selected from the memory cell array, and latch circuits are provided in the addressing section and the data transferring path for temporarily storing address decoded signal and write-in and read-out data bits in response to latch control signals higher in frequency than the system clock signal, thereby controlling the data stream in a pipeline fashion.

Abstract: An amplifier for sound signals is made up of an even number of power amplifiers each of which have each an output, wherein each amplifier output can be switched to a first terminal of an associated loudspeaker and in which the second terminals of the loudspeakers can be switched to an output of a buffer amplifier. In order to minimize power losses, the buffer amplifier supplies at its output a DC voltage which is about half the value of the supply voltage of the power amplifiers. In addition, half the power amplifiers supply an output signal that is inverted relative to their input signal.

Abstract: An adjustable current source circuit of a phase locked loop (PLL) circuitry fabricated on a single substrate provides a first current that is a function of an error voltage proportional to an amount of a phase difference of a comparison of a reference signal and a feedback signal. The circuit includes a first current source coupled to receive a second current from a reference phase locked loop of the PLL circuitry for providing a first portion of the first current under control of the second current. The first portion of the first current is proportional to the second current. A second current source is coupled to receive a third current from a transconductance amplifier of the PLL circuitry for providing a second portion of the first current under control of the third current. The second portion of the first current is proportional to the third current. A third current source provides a third portion of the first current selectively proportional to one of the second and third currents.

Abstract: The invention provides a high power, low distortion, high efficiency ampler design incorporating a high efficiency switching amplifier used in conjunction with a linear difference amplifier. The high efficiency switching amplifier, typically of full or half bridge design, is designed to generate a high efficiency, arbitrarily formed, wave portion such as a square wave. The high efficiency waveform is scaled down and is compared to a desired reference, such as a sinusoid. The output of the comparison is the analog difference (mathematical subtraction) between the reference waveform and the scaled-down switch amplifier output wave. This "difference" signal is then used to drive the linear difference amplifier which simply scales the signal linearly. The two power signals, one from the switching amplifier and the other from the linear difference amplifier, are then summed magnetically.

Abstract: A nonvolatile semiconductor memory device for use as a flash EEPROM includes a plurality of sectors each comprising a plurality of main memory cell regions each composed of a matrix of nonvolatile memory cells and at least one redundant memory cell region composed of a matrix of nonvolatile memory cells. When one of said nonvolatile memory cells in any one of the sectors is found defective and is selected by addressing, it is replaced with one of the nonvolatile memory cells in the redundant memory cell region.

Abstract: An active filter circuit (10) that has a cut off frequency being substantially independent of absolute and temperature variations due to on chip resistors (R.sub.1, R.sub.2 and R.sub.3) has been provided. The active filter includes a transconductance gain amplifier (16) having first and second currents (I.sub.B and I.sub.E) the ratio of which are controlled such that the absolute and temperature effects of any on chip resistors of the active filter circuit are removed. The ratio of the first and second currents of the transconductance gain amplifier are controlled by a circuit that generates third and fourth currents (I.sub.b and I.sub.e) which are a function of a bandgap voltage. The circuit then utilizes the third and fourth currents and provides, to the transconductance gain amplifier, a current that is substantially equal to the ratio of square of the third current to the fourth current, and a current substantially equal to the fourth current.

Abstract: Electrical data is recorded and retrieved by producing and detecting impedance change. A layer of high resistivity material on a conductive substrate is used as the recording layer. A conductive probe pressing on it is used for sending writing or reading electrical current flowing in a direction normal to its surface. A large enough electrical voltage pulse is applied on this probe, causing electro-forming in a data spot in the recording layer under the probe, turning the local resistance of this data spot from high to low. This change in resistance or more generally, change in impedance, is utilized to write data. Several kinds of impedance detecting circuits, utilizing the principle of voltage divider circuit or field effect transistors are employed in data reading. A large number of writing/reading units can be integrated compactly.

Abstract: A combination driver/summing circuit for rail-to-rail operation of a differential amplifier includes a differential amplifier input stage that amplifies an input signal and a current control circuit that regulates the operating currents through the active elements of the differential amplifier input stage. A summing circuit divided into first and second segments and supplied with current from a single common floating current source combines internal currents supplied by the differential amplifier input stage. A class A-B driver/output stage is coupled to the summing circuit to derive at least one output signal representative of the input signal and which is operative over nearly the full rail-to-rail supply voltage range.

Abstract: A random access memory device has memory cell blocks, row address decoders respectively associated with the memory cell blocks, sense amplifier circuit arrays each shared between two of the memory cell blocks, and a column selecting unit for transferring a data bit from one of the sense amplifier circuit arrays to an output data buffer circuit, a flag generating unit for producing flag signals indicative of memory cell blocks supplying the data bits presently stored in the sense amplifier circuit arrays, and an address discriminating unit operative to examine block and row addresses supplied from the outside thereof to see whether or not an accessed data bit has been already stored in the sense amplifier circuit arrays, thereby allowing the shared sense amplifier circuit arrays to serve as a cache memory.

Abstract: Controlling transient responses in power amplifiers may be accomplished in the following manner. Upon detecting an output power adjustment request, a reference level is accessed from memory, wherein the reference level is based on a previous output condition that is substantially equal to the requested output condition. From the reference level, a first response time is calculated and supplied to a control circuit of the power amplifier such that the power amplifier operates at a first gain level. When the first response time elapses, the power amplifier operates at a second gain level, where the first gain level is greater than the second gain level.