Abstract: A simple circuit for converting the resistance variations of a strain gauge measuring bridge into a frequency variation of an oscillator. The circuit includes first and second phase shift circuits connected in cascade in a feedback loop with a frequency-independent device having a variable gain factor F connected in parallel with the first phase shift circuit. The first phase shift circuit includes a high pass filter and a summing amplifier and the second phase shift circuit includes an all-pass filter circuit.

Abstract: A method and apparatus for controlling a plurality of subsystems (66, 70) associated with an agricultural vehicle such as a tractor. Examples of such subsystems in a tractor are hitch positioning, power take off (PTO), multiple range transmissions, differential lock, diesel fuel injection, and the like.A unified control system is provided including a central control unit having a first microprocessor (56) and a plurality of subservient control units each having a microprocessor (58, 60). Each of the subservient control unit microprocessors (58, 60) are connected for controlling at least one subsystem (66, 70) and for sensing the operating conditions of at least a single subsystem (66, 70) using sensors (68, 72). The subservient control unit microprocessors (58, 60) are also connected to the central control unit microprocessor (56) which controls communication between the subservient control unit microprocessors (58, 60).

Abstract: A raster graphic refresh memory architecture offering increased access speed. The memory takes advantage of the "page mode" of operation of dynamic random-access memory integrated circuit devices which require two separate device addresses for random access to a storage location therein but permit in "page mode" a first address corresponding to a set of storage locations to be maintained while changing the second address for more rapid access. The memory is organized so that a portion of the second device address is allocated to the least significant bits of one dimension of the display address and another portion of the second device is allocated to the least significant bits of another dimension of the display address, thereby forming a two-dimensional cell of storage locations on a single page corresponding to a region on the display.

Abstract: A memory management system for providing memory protection for various programs running in a computer such as a 16-bit multi-tasking computer system. The scheme of the present invention provides address translation so as to provide separation of memory spaces. In this connection, each program in the machine has associated therewith, two numbers including an offset number and a limit number. Each program is written so that its base starting address is at the same predetermined address, preferably zero. The address space for each program is separated in memory by adding the offset number for that program to the base address to provide the physical address number. The program is prevented from accessing any memory area outside of its allotted area by comparing the sum of the offset and processor addresses to the limit number.

Abstract: The invention relates to a hand-held computer comprising a peripheral frame which contains all the connections and in which cards are removably plugged. A flat display, mounted on said frame, is topped by a transparent plate which forms a matrix of touch-sensitive areas or points. The matrix is also mounted on the frame. The screen and the plate occupy the maximum of the upper surface of the casing and are electrically connected to the other circuits of the computer by contact with the frame on which they are mounted. The computer may be provided with phoneme recognition means, with hand-writing recognition means or with TV or radio receiving means by insertion of appropriate cards.

Abstract: A distributed automated control network system consisting of a master host computer, network processing nodes for monitoring and control of work locations and a subhost node which interfaces the nodes and host computer. The subhost includes dual microprocessor configurations on a common bus, one for communications and one for control, operating 180.degree. out of phase. Each node can be configured from a variety of modular subsystems on a common bus including modules for network control, data acquisition, digital and analog inputs and outputs, display terminals and the like in accordance with system requirements. The nodes communicate via two fiber optic channels, one operating clockwise and the other counterclockwise with foldback capability in the event of a fault. A conventional signal back-up is also provided.

Abstract: Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserved memory area associated with the currently active operating system is then addressed and register contents of a central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory and, data establishing the decor of the operating system being activated are entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun.

Abstract: Allocation of space of peripheral storage devices to host processes is based upon free or unallocated space in each such device. The device, irrespective of capacity, having the largest free space is most likely to receive a next space allocation. A central record in a multi-host system stores free space indications. In a disk storage device free space is indicated by the number of unallocated data storage record tracks for each such device.

Abstract: An electronic cash register comprises a memory having a plurality of registering regions each allotted for each of the commodity departments, and a keyboard including numeral keys, whereby any of the registering regions of the memory are set to be utilizable by means of the keyboard. If and when a series of the commodity department codes are consecutive, the first commodity department code and the last commodity department code are entered by the keyboard, while the restricted number of digits of the unit prices being registerable is also entered. The registering regions corresponding to the respective commodity department codes between the first commodity department code and the last commodity department code are in succession designated by an address counter, and the restricted number of digits of the unit prices is loaded in the designated registering regions, whereby the series of the consecutive registering regions are set to be utilizable.

Abstract: In a data processing system, a stack mechanism creates a stack of operands in a series of memory locations. The memory locations are grouped into stack frames corresponding to the operands included within individual procedures executed by a processing unit of the data processing system. The stack has a maximum number of allocatable storage locations with the actual physical size of the stack being equal to the total number of operands stored therein. The size of the stack is dynamically alterable to conserve usable storage locations in the memory and accessing of operands within a stack frame can be relative to the top or bottom of the stack frame.

Abstract: A replaceable intermediate socket and plug connector for a solid state data transfer system characterized by recording means for receiving digital data from a source of a train of electrical pulses and for delivering a desired digital data format, a magnetic memory cartridge pluggable into the recording means for receiving the digital data format, reader means into which the cartridge is subsequently plugged for receiving digital data format and for transferring the format to a data storage device, and replaceable intermediate connector means disposed between the cartridge and the reader means, so that the connector means is replaceable from time to time for maintaining integrity of reliable data retrieval via the cartridge.

Abstract: An audio/video editing system presents different menus of editing functions on a display screen and changes the menus as well as performing different editing functions in response to the touching of selected areas of the display screen by an operator. An arrangement of light emitting diodes and photodetectors provides a network of beams across the face of the display screen. Selected beams are interrupted when the operator points his finger at particular characters being displayed on the screen. The display menus and editing functions are controlled by an edit controller which includes a central processing unit having a memory loaded with data from a computer file system, a character generator for providing the various menus on the display screen and a plurality of intelligent line controllers coupled to a plurality of source tape recorders, a record tape recorder and a switcher capable of coupling a different one of the source recorders to the record recorder.

Abstract: The disclosure provides a general purpose register (GR) mask which associates predesignated address spaces with respective GRs assigned to contain a base value for calculating logical addresses within the address spaces. An address space mask register has a plurality of digit positions which receive the respective digit values comprising a particular GR mask. A respective digit position is selected by a base GR address signal provided by a storage address request from a CPU instruction decoder. The particular value of the selected digit in the mask register controls the selection among a plurality of STO registers, which designate a plurality of simultaneously available address spaces. The selected base GR is used in a System/370 B, D or X, B, D type of logical storage address representation. A base GR explicitly contains an intra-address-space base value.

Abstract: A data communication system in which a host data processing system is responsive to an automated sequence of data processing request signals from a remote data processing system. The remote data processing system includes a means for generating and storing in a nonvolatile read/write memory a log on signal which initiates the communications and causes the host system to be responsive to the remote system, a plurality of data processing request signals specifying operations to be performed by the host system and a log off signal for terminating the data communications. Special data processing request signals may include a predetermined delay before transmission of the next data processing request signal by the remote system or may require the host system to transmit a predetermined response signal in order to enable continuation of the sequence of data processing request signals from the remote system.

Abstract: A freely programmable control system is disclosed which includes a computer, a data memory, and a program memory, as well as a program controllable logical network for individual bit processing and an individual bit memory. The disclosed control system operates as an integrated system which utilizes both commands for the computer and separate commands for individual bit processing. Both types of commands are stored in the program memory as an integrated program. During individual bit processing the commands for the individual bit operations are routed from the program memory to the logical network circuit for individual bit processing, and are there executed. Similarly, during computer processing the commands for the computer are transferred directly to the computer and are there executed.

Abstract: A data communication system for controlling communications between a host data processing system and a remote data processing system. The host system communicates a plurality of output condition data signals to the remote system for storage therein. The host system then specifies the recall and output of the condition data signals previously stored in the remote system by transmitting corresponding condition name signals. The host system specifies whether condition data signals or condition name signals are to be sent to the remote system. The host system may send a predetermined number of condition data signals for storage at fixed sequential addresses within the remote system or the host system may specify particular addresses for storage of particular data signals in a memory within the remote system which has previously stored therein a set of default condition data signals. The remote system may include a means for repeating outputs specified by the host system.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source for table look-up for accumulator addressing, for example. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. The on-chip program memory may be disabled and only off-chip memory used for program fetch in a systems emulator mode. A non-maskable interrupt procedure used in the emulator mode generates a vector address for the on-chip ROM in switching between memory expansion and emulator modes, using an overvoltage detector to signal this condition.

Abstract: The decentralized arbitration device of the invention comprises an arbitration unit associated with each processing unit. This arbitration unit comprises an individual elementary arbitrator and a level elementary arbitrator. Their outputs are connected to a comparator which compares their output signals with the code of the unit considered, which code is supplied by a coding identification circuit. The individual priority request terminals of the units in the same level are connected together and the level priority request terminals of all the units are connected together.

Abstract: A portable word processor incorporates a keyboard for typing-in data relating to a textual document, a microprocessor for processing the data, and a microcassette recorder for storing each page of the textual data when typing of the page is complete. A half-line character display is situated on an operating panel of the word processor above the keyboard. The microprocessor includes a text buffer memory having a capacity corresponding to one page, favorably 1800 characters or 66 lines. A cassette recorder interface is included to control operation of the cassette during transfer of textual data from the text buffer memory for storage on the microcassette tape, and transfer of the data to the text buffer memory from the tape for editing and revision of the textual document. The microcassette recorder can store pages of the textual data intermittently with voice recording, such as dictation, on the same tape.

Abstract: A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory contiguous.