Abstract: The invention provides a method and system for persistent context-based behavior injection in a computing system, such as in a redundant storage system or another system having a layered or modular architecture. Behaviors that are injected can be specified to have triggering conditions, such that the behavior is not injected unless the conditions are true. Triggering conditions may include a selected ordering of conditions and a selected context for each behavior. In a system having a layered architecture, behavior injection might be used to evaluate correct responses in the face of cascaded errors in a specific context or thread, other errors that are related by context, concurrent errors, or multiple errors. Behavior injection uses non-volatile memory to preserve persistence of filter context information across possible system errors, for reporting of the results of behavior injection, and to preserve information across recovery from system errors. Multiple behavior injection threads are also provided.

Abstract: Systems and methods for detecting and correcting errors in programmable logic ICs are provided. In one embodiment, a scrubber periodically reads the memory cells in a programmable logic IC, detects and corrects any errors, and writes the corrected contents back into the memory cell. In another embodiment, regions of memory cells in a programmable logic IC each have associated error correcting circuitry which operates to continuously detect and correct errors as they occur. Error correcting circuitry can further be designed to reduce static hazards. It may be more desirable to design programmable logic IC routing architectures that reduce the number of memory cells needed to implement a given function. Error correcting circuitry can be provided for configuration memory or for an embedded memory block on a programmable logic IC.

Abstract: A method, a system, and a network entity enable a detection of a connection fault and perform the switch-over in less than 50 ms. CV packets are being sent, for example, 1/10 ms (1 CV packet per 10 ms) or 1/15 ms (1 CV packet per 15 ms). The interval of the CV packets, consequently the frequency for sending CV packet, can be any interval that makes the switch-over time for a protected substantially real-time connection achievable. Moreover, the interval (the frequency) should be such that the interval makes the fault detection from the fault event to occur in less than 50 ms and triggers the switch-over to occur also in less than 50 ms from the occurrence of the fault event.

Abstract: A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit. The controller is configured to enable operation of the interfacing portion to provide communications between the first and second storage processors, sense a failure within the clock circuit, and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation. Such resetting of the interfacing portion prevents the remaining storage processor from locking up, thus freeing that storage processor so that it is capable of continuing to operate even after the failure.

Abstract: A network communication terminal apparatus compares a successive occurrence count number and a set threshold occurrence number of each error related to network communication operations, and when an error of which the successive occurrence count number is equal to the set threshold occurrence number is detected, an indication of the occurrence of this error is output to the user. In this way, the network communication terminal apparatus is able to accurately provide error indications that are relevant so as to secure reliability in the network communication operations of the apparatus while disregarding irrelevant error occurrences to avoid needless distractions.

Abstract: A secondary volume of a mirrored volume pair is replicated by suspending the mirroring operations, associating a selected volume identifier with the secondary volume, replicating the secondary volume to a backup volume, and associating the original secondary volume identifier with the backup volume. In some embodiments the original secondary volume identifier is written to a hidden field on the secondary volume and the hidden field is copied to the backup volume identifier field after the replication. In some embodiments the actions of suspending the mirror operations, managing the volume identifiers, replicating the secondary volume to a backup volume, synchronizing the secondary volume with the primary volume, and reestablishing the mirror pair are performed as an automated sequence. The resultant replication method is less costly and error prone because it may be created by an automated process rather than manual commands issued by a system administrator.

Abstract: A method capable of detecting a status of a basic input/output system (BIOS) for setting a clock is applied to a clock generating device of a computer motherboard and sets the clock according to a signal status of the BIOS or a trigger signal. A device capable of detecting the BIOS status for setting the clock is also proposed. The device has a crystal oscillator, a frequency control unit, a phase-lock-loop (PLL) spread-spectrum unit electrically connected with the crystal oscillator and the frequency control unit, a memory unit having a clock setting value stored therein, a detection control unit electrically connected with the memory unit and used to detect a signal status, and a logic control unit electrically connected with the PLL spread-spectrum unit, the frequency control unit and the detection control unit.

Abstract: A method of and system for troubleshooting a first computer system using a second computer system having a processor and a memory storing an electronic document including troubleshooting information and storing a set of troubleshooting commands for execution by the first computer system is described. The troubleshooting command set is related to the troubleshooting information contained in the electronic document. A method of generating an electronic document including troubleshooting information and a set of troubleshooting commands for execution by a first computer system is also described.

Abstract: Systems and methods are provided that prevent faulty drivers from being loaded and/or can prevent faulty drivers from being installed. Thus, instability of a computer system can be mitigated. Additionally, the occurrence of data corruption, system halting and the like can be reduced. A requested driver is compared to a list of faulty drivers from a faulty driver database. If the requested driver is in the list of faulty drivers, the requested driver is deemed faulty or defective, and is prevented from being loaded. Additionally, if the requested driver is in the list of faulty drivers, the requested driver can be prevented from being installed. Otherwise, the requested driver is operable and can be installed and/or loaded.

Abstract: A multiple disk system comprises plural physical drives organized as plural groups of disks. Each group is accessed as a plurality of logical volumes. One of the logical drives is considered a primary volume and one or more other logical volumes are considered as secondary volumes, which together constitute a mirroring group. Data contained in a memory records such organization. The data is consulted to select a secondary volume when the disk group containing a primary volume fails.

Abstract: A sequential operation system component (e.g., shell) testing method is disclosed that utilizes a set of established user applications to access particular components of an operating system. A set of components of the operating system to be tested are established. Capabilities of a set of applications to access the components is established. The manner in which applications access the components is analyzed to establish classes. Furthermore, parameter sets are identified for each of the classes (e.g., functions). Test cases are created based upon combinations of parameter usages. Test calls are formulated by defining actual values to the parameter usages defined for the test cases.

Abstract: A Fieldbus device and method for handling errors arising from parameter write messages. A load mode identifier detects if the parameter write messages are operator initiated or program initiated. If program initiated, communication of errors resulting from execution of the parameter writes is suppressed. Also, a rejection of a parameter write operation arising from the errors is suppressed for program initiated program write messages.

Abstract: Methods and apparatuses that automatically determine the capabilities of UPS devices. Systems automatically determine whether a UPS device is capable of protecting system resources by comparing the UPS capabilities against system requirements. Such systems can use that determination to approximate how long a UPS device can reliably supply power. Systems having multiple UPS devices can be implemented such that the connections of the UPS devices to system resources are automatically determined, the load on each UPS device can be found, the capabilities of the UPS devices can be obtained, a comparison between UPS load and UPS capabilities can made, and a warning of problems can be sent. Using UPS capability and load information a system can provide for a controlled shutdown of system resources.

Abstract: In one embodiment, the invention may include a logic structure integrated in an integrated circuit (IC), that has a set of bus inputs to generate events, a mask register to select inputs from among the set of bus inputs, a logic register to select logic to apply to the selected inputs and an event output to supply the result of the applied logic. The embodiment may further include a bus interface integrated in the IC and coupled to the logic structure to transmit settable parameters to the mask register and the logic register of the logic structure from an external agent.

Abstract: A method of recovering a stripe of erasure coded data begins with sending query messages to storage devices. The method continues with receiving query reply messages from at least a first quorum of the storage devices. The query reply messages include a minimum number of the stripe blocks needed to decode the stripe. Following this, the stripe of erasure coded data is encoded. Next, a write message is sent to each of the storage devices, which include a timestamp and the stripe block destined for the storage device. The method concludes with receiving a write reply message from at least a second quorum of the storage devices indicating that the stripe block was successfully stored. The first and second quorums each meet a quorum condition of a number such that any two selections of the number of the stripe blocks intersect in the minimum number of the stripe blocks.

Abstract: In a command line environment, an error object is used to store information about each occurrence of an error during processing of a command-line instruction. In an object-based command line environment, each command in a complex command-line instruction stores sufficient information in the error object to completely describe the error. That information may be later used either by subsequent commands or in conjunction with another command-line instruction to further process the unprocessed resources.

Abstract: An embodiment of the present invention is a method for monitoring various data sources for events indicative of a current or potential system health problem, thereby detecting positive or negative trends in system health data. At the core of this module is an algorithm that analyzes a series of data points that have been collected into sample sets over time.

Abstract: An apparatus and method for controlling and providing a robust, single entry cache memory is described in connection with an on-board cache memory integrated with a microprocessor. By implementing the single entry cache memory in a redundancy array of the cache memory, CPU debug procedures may proceed independently of the cache debug by disabling part of the cache memory and enabling a dedicated single entry cache in the redundancy array. Use of a cache redundancy array for the single entry cache imposes no area or latency penalties because the existing cache redundancy array already matches the latency of the cache.

Abstract: A method and apparatus to recover a set of data from a full backup and an incremental or differential backup are described. This includes a source directory that was modified between the full backup and the incremental or differential backup. The full backup is restored, including the source directory, and a new directory is created to replace the restored directory when the incremental or differential backup is applied to the restored full backup. Content for an entry from the modified source directory in the incremental or differential backup is created in the new directory if the corresponding content is present in the incremental or differential backup. If the content for the entry is not present in the incremental or differential backup, then the entry in the new directory is linked to corresponding content in the restored directory from the full backup.

Abstract: In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.