Abstract: A digital multi-phase clock generator includes a reference clock input and first and second digitally-programmable delay lines. The first and second delay lines are coupled in parallel with one another, in series with the reference clock input. Each delay line includes a delay control input. The first delay line has a plurality of phase outputs which are synchronized with the reference clock input and have different phases from one another. The generator further includes a phase detector and a delay control circuit, which are coupled with second delay line to form a phase-locked loop. The delay control circuit has a digital delay control output, which is coupled to the delay control inputs of both the first and second delay lines. The phase-locked loop adjusts delay through the first and second delay lines to lock a phase of an output of the second delay line to a phase of the reference clock input.