Abstract: Non-intrusive performance monitoring of a DS0 channel between a customer premises interface and a D4 channel bank includes an augmentation of existing channel bank equipment and a digital services communication device terminating the DS0 link at the customer site. An auxiliary signalling and performance monitoring arrangement is remotely accessible by a non-resident control site, thereby enabling the control site to perform prescribed network supervisory tasks with respect to one or more selected DS0 links. Office channel unit data port and line interface components of the channel bank are modified to provide bidirectional signalling capability via the receive segment of the channel bank's internal communications link.

Abstract: A method and apparatus for increasing the resolution of a pulse width modulated signal representative of a measured parameter such as the pressure measured by a pressure cell. The analog signal from the pressure cell is converted to a digital signal using a predetermined clock frequency. The digital signal is scaled to 2.sup.N (N is an integer greater than or equal to one) times the clock frequency and the N lowest order bits are checked to determine if they are a one or a zero. A one is added to the least significant bit of the scaled digital signal in a predetermined manner in the next N consecutive cycles of the scaled digital signal dependent upon the which of the N lowest order bits are a one.

Abstract: The receiver processing circuitry performs the steps of an iterative process and in each step derives from a received signal Iin a threshold value related to a characteristic of the signal. This value is stored via an analog-to-digital convertor AD in a memory MEM. The characteristic of the signal Iin is then compared in a comparator consisting of two comparator circuits C1 and C2 and a switch S, with a threshold value stored previously for the substation which sent Iin. This value is prior to receipt of Iin, i.e. during a previous timeslot, applied to, e.g., C1 via a digital-to-analog convertor DA1. During this comparison a threshold stored for the substation which is next to transmit a signal is retrieved from MEM via a digital-to-analog convertor DA2. The result of the comparison is via S generated at Dout and represents the digital conversion of Iin. The power of the transmitted signals is controlled by a circuit included in the transmitters of the system.

Abstract: A method and apparatus for performing color compression uses human factors to weight a distance metric in order to select a set of k presentation colors to represent n colors in an original image, where n>k. This same distance metric is used as part of a process to select an optimal mapping of the original image pixels to the presentation colors. The presentation colors are selected based upon a data clustering scheme in which clusters of colors are selected based upon their respective distance from each color within a given cluster and from colors in other clusters. Colors in different clusters are required to be farther apart than colors in the same clusters. This accounts for colors with high importance in accurately presenting the presentation image but having low overall occurrence in the image file.

Abstract: A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

Abstract: A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

Abstract: An acoustic displacement flowmeter uses a high-compliance acoustic-type displacement transducer to measure fluid flow accumulated by temporarily restricting the flow of a fluid along a path. The displacement transducer signal, representative of fluid flow rate, is integrated after an initial settling period elapses, and the integrated signal is periodically sampled. The number of samples taken during a measurement cycle depends upon the slope of the integrated signal and the maximum sample period permitted. The samples are summed and the actual flow rate is computed by a microcomputer.

Abstract: A phase locked loop has an average zero phase start circuit to detect and correct for the average phase difference between a data signal and a VCO clock signal over a short interval at the beginning of phase-lock acquisition. The average zero phase start circuit has a data comparator to split the data stream into odd and even portions; odd and even pulse position detectors to detect the phase difference between pulses of the odd and even data signals and corresponding pulses of the VCO clock; and a ramp generator to generate a voltage corresponding to the sum of the detected phase differences. The ramp generator employs a capacitor and switched current sources that discharge the capacitor at a fixed rate to generate the voltage. After 4 phase difference measurements are taken, the VCO is stopped, and another current source discharges the capacitor at 4 times the fixed rate.

Abstract: A VSLI transceiver chip incorporating an improved analog PLL circuit for recovering a digital clock signal from a digital data signal having pulse widths which may vary during each data cycle. The analog PLL clock recovery circuit comprises a phase detector, a gain control circuit, a variable current charge pump, a loop filter and a variable frequency oscillator. The phase detection means for detecting, during each data cycle, the phase error between the digital data signal and recovered digital clock signal, and produces first end second digital control pulse signals in response to the detection of the phase error. The gain control means produces third and fourth digital control pulse signals during each data cycle.

Abstract: A one-bit differential detector for a GMSK signal operates independently of an offset frequency. In particular, a decision signal used by a decision circuit to distinguish between logic "0" and logic "1" is always equal to sin[.DELTA..phi.(T)]. The inventive detector has an improved bit error rate performance in comparison to the prior art.

Abstract: A method of lossless data compression for efficient coding of an electronic signal of information sources of very low information rate is disclosed. In this method, S represents a non-negative source symbol set, {s.sub.0, s.sub.1, s.sub.2, . . . s.sub.N-1 } of N symbols with s.sub.i =i. The difference between binary digital data is mapped into symbol set S. Consecutive symbols in symbol set S are then paired into a new symbol set .GAMMA. which defines a non-negative symbol set containing the symbols {.gamma..sub.m } obtained as the extension of the original symbol set S. These pairs are then mapped into a comma code which is defined as a coding scheme in which every codeword is terminated with the same comma pattern, such as a 1. This allows a direct coding and decoding of the n-bit positive integer binary digital data differences without the use of codebooks.

Abstract: A mass flow meter includes a body having a cylindrical bore and an elongated cylindrical piston positioned in the bore concentrically therewith. An elongated annular fluid flow channel of uniform depth is bounded by a cylindrical surface of the piston and a surface of the bore. Fluid flows laminafly through the channel. First and second concentric ferrules are located at first and second end portions of the piston to precisely position and hold the piston concentrically in the bore, by elastically expanding in response to longitudinal forces on the first and second end portions of the piston to symmetrically engage a wall of the bore. A first pressure measuring probe in fluid communication with an upstream equalization chamber measure fluid pressure in the upstream equalization chamber, and a second differential pressure transducer in fluid communication between the upstream equalization chamber and a downstream equalization chamber measures differential fluid pressure between the two equalization chambers.

Abstract: In a timing extraction device coupled to a demodulator which derives a real signal component and an imaginary signal component from a signal received via a transmission line, a band-pass filter extracts a 1/2-Nyquist frequency from either the real signal component or the imaginary signal component. The 1/2-Nyquist frequency includes two symmetrical frequency components. A vector conversion unit processes the 1/2-Nyquist frequency so that a vector signal corresponding to one of the two symmetrical frequency components of the 1/2-Nyquist frequency is output from the vector conversion unit. A square multiplier squares the vector signal received from the vector conversion unit and thereby generates a phase error signal indicating timing information concerning the analog signal. The phase error signal has an angle which is double an angle of the vector signal.

Abstract: A method and apparatus for concurrent communication of analog information and digital information. In general terms, when the communication channel is viewed as a multi-dimensional space, the digital information signal is divided into symbols, and the symbols are mapped onto the signal space with a preset distance between them. The analog signal, generally limited in magnitude to less than half the distance separating the symbols, is converted to component signals and added (i.e., vector addition) to the symbols. The sum signal is then transmitted to the receiver where the symbols are detected and subtracted from the received signal to yield the analog signal components. The transmitted analog signal is recreated from those components. Both half-duplex and full-duplex operation is available in accordance with this invention.

Abstract: A dc-coupled packet mode digital data receiver, for use with an optical bus uses peak detectors to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A dc compensator, responsive to outputs of the peak detectors, shunts dc or low frequency currents, corresponding to "dark level" optical signals, from the input of the receiver.

Abstract: A high frequency transmitter comprises a large number of narrowband channels spaced over a broad bandwidth transmission. In one arrangement input data to be transmitted is demultiplexed (1101) so that sections of data are transmitted in groups of channels at 50 baud (say), each 50 baud channel produces a number of diversity channels modulated using difference phase shift key (DPSK) (103) and then added (105) for transmission. In the receiver, coherent summation (803) of close-bunched channels can be used and semi-coherent channel addition (805) can be used across the complete bandwidth. The received signal is convened to digital form then processed by an FFT circuit to produce frequency bins corresponding to the transmitted diversity channel frequencies. DPSK demodulation is carried out and running averages are carried out in each channel to determine the proportion of times that the phase difference falls within allowed limits (907).

Abstract: A data synchronization system (12) for use with a first and a second device has control circuitry (34), first circuitry (36, 38, 40, 42 and 44) and second circuitry (32). The control circuitry generates a first and a second control signal. The logic states of the two control signals depend upon the ratio of the clock frequencies of the two devices. The first circuitry receives a first data signal from the first device and generates a first output signal for the second device depending upon the logic state of the first control signal. Conversely, the second circuitry receives a second data signal from the second device and generates a second output signal for the first device depending upon the logic state of the second control signal. The synchronization system may be incorporated into data processing systems in which the data processor and bus operate at different clock frequencies.

Abstract: Digital signal transmission system which operates by coded modulation of a constellation, the system comprising an encoder (5) which includes a modulator (13) installed at a transmitting station, and a decoder (105) which includes a demodulator (113) installed at a receiving station. A multistage channel encoder (12) carries out a concatenation of internal and external codes to blocks and divides the coding over various partitioning levels of the constellation. The coded symbol blocks are subjected to the work of a frequency-division interleaver (37), the modulator (13) operating according to an orthogonal carrier frequency-division multiplexing technique. The decoder (105) includes circuitry to carry out reverse operations to those carried out for the coding.

Abstract: An image processing system is capable of image compression including smoothing and edge detection for representing an image with a minimal amount of data and image reconstruction from the minimal data. The system comprises an array of pixel locations having intensity data representing the intensities of an image. The system also comprises a processor having a smoothing module for iteratively smoothing the intensity data to eliminate noise associated therewith. The processor also has an edge detection module for iteratively detecting pixel locations defining edges of regions of substantially constant intensity across the image. The processor further comprises a reconstruction module for reconstructing the image from the pixel locations defining edges and the intensity data associated with said pixel locations.

Abstract: A communication system segment having phase multiplexing. A first communication station contains a data source which sequentially outputs a series of data signals during a series of clock periods. The data source outputs one data signal from the series during each clock period. The first communication station also contains a transition buffer which has an input connected to the output of the data source. The transition buffer has a first-in, first-out mode in which the transition buffer stores a series of Q data signals output from the data source during the most recent Q clock periods, where Q is an integer greater than zero. A second communication station contains a data receiver which sequentially inputs a series of data signals during a series of clock periods. The data receiver inputs one data signal from the series during each clock period. A communication line connects the output of the data source to the input of the data receiver.