Patents Examined by Timothy J. Sutton
  • Patent number: 6508845
    Abstract: A method and apparatus for precoining a ball grid array (BGA) type package prior to electrical characterization of the package employs a heated pressing plate with a smooth, flat bottom. The heated pressing plate is controllably pressed against a plurality of solder balls attached to a chip scale package. The heated pressing planarizes the tops of the solder balls, thereby evening out height differences among the solder balls. With the height differences evened out, a grounding plate of a test fixture can be applied on the array of solder balls and reliably contact each of the solder balls that are to be grounded, regardless of their initial height differences.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: January 21, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Eric S. Tosaya
  • Patent number: 6489255
    Abstract: A layer of doped oxide glass is deposited on a semiconductor device in a chemical vapor deposition chamber by reacting gaseous sources of silicon, ozone and at least one boron or phosphorus dopant in a carrier gas, the ozone being present in a ratio of about 9-15 weight percent of the carrier gas. The deposited layer of doped oxide glass contains no greater than about 4 weight percent each of boron and phosphorus concentration and is annealed at a temperature no greater than about 700° C. for a time sufficient to soften and outgas any residual moisture in the oxide glass layer and level the upper surface to a desired degree.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: December 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Son Van Nguyen, Christopher Joseph Waskiewicz, Donna Rizzone Cote
  • Patent number: 6482732
    Abstract: A method for polishing a semiconductor wafer, includes the steps of supplying a polishing slurry between a polishing pad and a semiconductor wafer; polishing a surface of the semiconductor wafer with the polishing pad in a CMP process; and controlling the temperature of the polishing slurry to be in a range between 2° C. to 10° C. while the semiconductor wafer is polished.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: November 19, 2002
    Assignee: OKI Electric Industry Co., Ltd.
    Inventor: Shunichi Tokitoh