Abstract: A plurality of identical circuit board identification generators are individually located on an associated plurality of circuit boards in a computer system, each generator providing a unique identification for each associated circuit board. Identification numbers are automatically and sequentially generated by the generators upon the initial system turn on or upon a resetting of the system. The generators comprise a counter and logic circuitry for enabling the counters. The counters are initially disabled and pre-set to a maximum count. The first counter is then enabled and counts from the maximum to zero, and delivers an enable signal to the logic circuitry in the next circuit board to enable that counter. The enable signals propagate from board to board until the last board commences its count, at which time all counters are disabled. In this manner, N circuit boards will be identified as boards "O" through "N-1.

Abstract: The present invention relates to a high speed optical switch and the use of such switches to form a time division demultiplexer. The optical switch comprises a length of linear material (12) including an outer surface on a portion of which is formed a layer of nonlinear material (11) to form a nonlinear interface (10) at the boundary of the two materials. An input data light beam (14) is propagated in the linear material with a predetermined intensity and angle of incidence on the nonlinear interface to, by itself, cause total reflection of the input beam. A control light beam (11) is also selectively energized and directed at the nonlinear interface with an intensity and angle of incidence to cause a portion of the input data beam to be formed into a self-focused channel or beam propagating in the nonlinear material. The self-focused beam can then be detected at an edge of the nonlinear material.

Abstract: Image information stored on a recording medium is read out by photoelectrically converting light obtained by two-dimensional scanning of the image information, and integrating the electric signal by use of a plurality of integrators which are sequentially actuated each time a first clock pulse determining the picture element size is input. Integration periods are set not shorter than one clock length of the first clock pulse so that they partially overlap each other. The integration output is sampled by a second clock pulse at a point of time within the overlap region of the integration periods but outside regions where the next integrator is in the integration start transient and where the currently operating integrator is reset. The integrator reset period is set to sufficiently reset each integrator and prepare for the next integration.

Abstract: A short term response enhancement for a digital phase-locked loop is implemented to provide a relatively major change in the phase of the output signal over a relatively short period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur, producing an output signal when the two numbers agree. The number of pulses which occur between successive cycles of the input signal are also compared against the previously determined average. A count which differs from the average count indicates a change in phase of the input signal.