Abstract: A pen-operable computer which also functions as a fully keyboard-operable computer. The keyboard contains an independent power supply, and is linked to the main chassis only by an infrared interface. The system chassis is very compact, but includes a full-width docking bay into which the keyboard can be latched for storage. When keyboard interface is desired, the user takes the keyboard module out of its docking bay and uses it in whatever position is most comfortable. When keyboard interface is not desired, the user simply snaps the keyboard module back into its docking bay for safe storage and/or transport.

Abstract: A system for performing parallel processing of digital data in order to compute numerical functions and extract characteristic information based on the digital data. After the digital data is processed by the parallel processing portion, a sequential processing portion rewrites the processing data according to a sequential processing operation so that operations such as thinning and labelling may be performed.

Abstract: The present invention includes a first-language basic input/output control program linked with a first-language OS an a computer and an input/output device for executing first-language application software in object code form, an emulator linked with second-language application software, the first-language basic input/output control program and the first-language OS for executing the second-language application software in object code form and a way of activating and terminating the emulator. Thereby, there is provided a computer system which permits the first-language application software and the second-language application software to be operated using the identical computer, input/output device and first-language OS.

Abstract: The present invention enables a computer system to store from register files to memory, and restore from memory back to the register files, data from programs designed to operate in accordance with a first word size, as well as programs designed to operate in accordance with a second word size. This is accomplished without an increase in hardware and without requiring modification of existing software. In particular, an indication is utilized at the procedure level to designate whether a particular procedure is using words of a first or second word size. Preferably, this indication is placed in a first predetermined bit position in the stack pointer of the procedure. When a save occurs, certain contents from the register file are saved to memory along with the stack pointer. Under certain circumstances, the word size indication is moved to a second predetermined bit position within the stack pointer which is stored in a predesignated stack pointer address in the save area.

Abstract: An instruction fetch unit in which an early instruction fetch is initiated to access a main memory simultaneously with checking a cache for the desired instruction. On a slow path to main memory is a large main translation lookaside buffer (TLB) that holds address translations. On a fast path is a smaller translation write buffer (TWB), a mini-TLB, that holds recently used address translations. A guess fetch access in initiated by presenting an address to the main memory in parallel with presenting the address to the cache. The address is compared with the contents of the TWB for a hit and with the contents of the cache for a hit. The guess access is allowed to proceed upon the condition that there is a hit in the TWB (the TWB is able to translate the logical address into a physical address) and a miss in the I-cache (the data are not available in the I-cache and hence the guess access of main memory is necessary to get the data).

Abstract: A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths.

Abstract: In the SIMD parallel computer according to the present invention, the arithmetic unit has an instruction storage means for storing a local instruction, a selecting means for selecting any one of the common instruction and the local instruction stored in the instruction storage means, a selection control means for controlling a selecting operation of the selecting means and a means for executing the selected instruction. In an arrangement of the SIMD parallel computer of this invention is that each arithmetic part is connected to the memory via an address changeover circuit and a data changeover circuit as well. One arithmetic part is selectively connected to the memory under the selection control handled by the central control circuit.

Abstract: A prefetch unit includes a Branch history table for providing an indication of an occurrence of a Branch instruction having a Target Address that was previously taken. A plurality of Branch mark bits are stored in an instruction queue, on a half word basis, in conjunction with a double word of instruction data that is prefetched from an instruction cache. The Branch Target Address is employed to redirect instruction prefetching. The Branch Target Address is also pipelined and follows the associated Branch instruction through an instruction pipeline. The prefetch unit includes circuitry for automatically self-filling the instruction pipeline. During a Fetch stage a previously generated Virtual Effective Address is applied to a translation buffer to generate a physical address which is used to access a data cache. The translation buffer includes a first and a second translation buffer, with the first translation buffer being a reduced subset of the second.

Abstract: A system and method for dispatching logical central processing units (CPUs) among physical CPUs in a multiprocessor computer system having multiple logical partitions, wherein the cryptographic facilities may not be interchangeable. According to the present invention, the logical CPUs are dispatched among the physical CPUs according to either an affinity, floating, or disabled scheduling method. The affinity scheduling method is used when the crypto facilities are not interchangeable or when non-interchangeable crypto functions are performed. The floating scheduling method is used when the cryptographic facilities are interchangeable and interchangeable crypto functions are performed. The disabled scheduling method is used when the logical CPU is not authorized to issue cryptographic instructions.

Abstract: Provides a software-to-software interface and a software-to-hardware interface between software users and a hardware ADM facility (ADMF) in a data processing system. Such software user presents only virtual addresses to the software-to-software interface in a MSB list. The user list defines virtual address spaces, including a "hiperspace", in a manner that represents physical backing media as different random-access electronic storages, such main storage (MS) and expanded storage (ES). The real data transfers are within or between the backing storages. The user list is transformed into an ADM operation block (AOB), which is assigned an ADM UCB in a UCB queue which is associated with an ADM subchannel. The software-to-hardware interface generates an ORB, containing the AOB address, as an operand of a SSCB instruction which is executed to queue the associated subchannel onto one of plural co-processor queues in the ADMF.

Abstract: An apparatus and method for matching information between a first and a second processor to preserve a call includes determination units each provided in the respective processor. When a communications link experiences a fault, the determination units determines whether or not information items, respectively, in first and second processors, are to be preserved. A transmission unit notifies a match unit in a second processor of a determination of the call preservation. The match unit in the second processor compares the received information with an information to be preserved by the information of the second processor, and notifies the first processor of a result of a match or a non-match. A first initialization unit and a second initialization unit initialize their information items, respectively in the first and second processors, based on the result.

Abstract: A processing system is configured for providing an external in circuit emulator with an internal execution state resulting from the execution by a first processor of an internal instruction stored in an internal instruction cache. The processing system includes a second processor which includes an internal instruction cache for also storing the internal instructions. The second processor is coupled to the first processor in a master/slave configuration to enable the second processor to duplicate the instruction executions of the first processor. The second processor includes an output for providing the internal execution state which is coupled to the in circuit emulator by an external address bus for providing the internal execution parameter to the in circuit emulator.

Abstract: A system and method for operating application software in a safety critical environment comprises providing a data processor having an operating system for effecting processing operations and an intermediate shell which interacts with the operating system and application software to emulate a safety critical environment to the application software. The application software is run by interacting solely with the intermediate shell to effect a safety critical environment therefor.

Abstract: A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the cache memory unit, produces the predecode bits for utilization by a superscalar processor. The circuitry of the predecode unit is comprised of logic and latches. The predecode unit includes two main paths for transporting instruction information: a predecode path and an instruction path. The instruction path buffers instructions sent from memory to cache as information from these instructions are decoded in the predecode path. The predecode path includes a decoder and a bit information unit. The decoder identifies the instruction type by monitoring the op-code of instructions entering the predecode unit. The bit information unit is coupled to the decoder and receives signals indicating instruction type and passes these signals through logic gates to obtain whether instructions can be bundled.

Abstract: An In Circuit Emulator includes first and second memories, a emulation chip, gate circuit, and an input circuit. The first memory stores a program to be executed by a target system. The second memory stores a program for controlling the emulation chip. The emulation chip emulates the target system, and includes: a first latch for latching an externally supplied supervisor interrupt request signal; a second latch for latching a macro service request; and a sequencer for selectively accessing the first and second memories in response to the supervisor interrupt request signal and the macro service request to execute a corresponding program, the sequencer executing the macro service request independent of the supervisor interrupt request signal latched in the first latch. The gate circuit outputs control signals for controlling access to the first and second memories. The input circuit directly inputs the macro service request latched in the second latch.

Abstract: An in-circuit emulator, alternatively referred to as a microcontroller debugging system, has a control processor having I/O ports and a multiplexed address/data bus port, an emulation processor having I/O ports and a multiplexed address/data bus port, an emulation memory having address inputs, a data bus interface and a plurality of two-to-one multiplexers. The in-circuit emulator is configured such that the control processor and the emulation processor each have at least one port directly coupled to the data bus of the emulation memory without the use of external tri-state buffers, this is referred to as the shared bus. An address latch, shared by both processors, has its inputs coupled to the shared bus. The outputs of the address latch form a portion of the emulation memory address input, and are coupled to a corresponding portion of the emulation memory address inputs.

Abstract: A method for establishing a spoofing service for a high-level file transfer protocol from a modem. A modem spoofing initiation protocol (MSIP) word containing modem limitations is appended to the initial negotiation frame sent by the host to the receiver. If the receiving modem detects the MSIP word at the end of the negotiation frame, it compares its own limits with the received limits, takes the lower limit as the agreement, then appends the agreement word to the frame sent to acknowledge the negotiation frame. If the sending modem detects the agreement word, both modems use the agreed limits to examine the maximum block size and window size in the negotiation frame of the high-level file transfer protocol. If the block size and window size are within the agreed values, the spoofing service begins.

Abstract: An inventive arbiter controls access to a resource in a high speed computer or telecommunications network. The arbiter is capable of performing round-robin scheduling for N requests with P possible priority levels with a sublinear time complexity. The high arbitration speed is achieved through use of a tree structure with a token distribution system for implementing the round-robin scheduling policy.

Abstract: A predictive caching system for use in computer system having at least one portion of memory in which information is stored for retrieval, a general cache used to speed the operation of accessing such memory, and a processor for controlling the access of the memory comprising apparatus for discerning a pattern of access of the memory, apparatus operating in response to the pattern determined by the apparatus for discerning a pattern of access of the memory for determining a next address which will probably accessed in such memory if the pattern discerned continues, and apparatus for storing the information at the next address determined prior to the next access of the memory whereby the information at the next address is available without the need to access the memory.

Abstract: Information about the location of untranslated instructions in an original program is discovered during execution of a partial translation of the program, and that information is used later during re-translation of the original program. Preferably the information includes origin addresses of translated instructions and corresponding destination address of untranslated instructions of execution transfers that occur during the execution of the partial translation. Preferably this feedback of information from execution to re-translation is performed after each execution of the translated program so that virtually all of the instructions in the original program will eventually be located and translated. To provide an indication of the fraction of the code that has been translated, the program is scanned to find plausible code in the areas of memory that do not contain translated code.