Abstract: First and second inverter circuits each include a P channel and an N channel MOS transistor whose current paths are connected in series between a power-supply and ground. An input terminal of the second inverter circuit is connected to an output terminal of the first inverter circuit. A first capacitor is connected between the output terminal of the second inverter circuit and the power supply. A second capacitor is connected between the output terminal of the first inverter circuit and ground. A third capacitor is connected between the output terminal of the second inverter circuit and the input terminal of the first inverter. A fourth capacitor is connected between the input terminal of the first inverter circuit and ground.

Abstract: A noise-suppression logic system suppresses a noise signal having a time duration which is less than a predetermined time. A delay circuit has a delay which is equal to the predetermined time. A logic combining circuit is coupled to the system input terminal and to the output terminal of the delay circuit. A R-S latch circuit, having a RESET input terminal, a SET input terminal, and an OUTPUT terminal provides a delayed output signal corresponding to an input signal which has a time duration greater than the predetermined time. A set circuit has a first input terminal coupled to the system input terminal, a second input terminal coupled to the output terminal of the delay circuit, and an output terminal coupled to the SET input terminal of the R-S flip-flop circuit.

Abstract: A noise removing circuit for removing an impulse noise in a signal. An input selector switch receives a first signal and a second signal to selectively output the first and second signals. A polyphase sampling pulse generator outputs polyphase pulse trains. A plurality of sample-and-hold circuits are in cascaded connection to sample and hold the output of the input selector switch. Each of the sample-and-hold circuits is activated by pulses of a corresponding phase of the polyphase pulse trains to sample and hold a signal level being held on a preceding circuit. Each of a plurality of multipliers has a predetermined multiplication coefficient and outputs the signal level on each of sample-and-hold circuits multiplied with said predetermined coefficient. An adder adds up the outputs of the plurality of multipliers to produce the second signal.