Patents Examined by Timothy R. Callahan
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Patent number: 7245177Abstract: This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.Type: GrantFiled: July 27, 2004Date of Patent: July 17, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Fujita, Motosugu Hamada, Hiroyuki Hara
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Patent number: 7242241Abstract: A reference circuit comprising first and second field effect transistors connected to form a first current mirror, and third and fourth field effect transistors connected to form a second current mirror, wherein a property of the first transistor is mismatched relative to the second transistor such that the threshold voltage of the first transistor is significantly higher than the threshold voltage of the second transistor, and the drain current versus gate-source voltage responses of the first and second transistors have substantially different gradients for current levels at which the reference circuit is operated.Type: GrantFiled: May 19, 2003Date of Patent: July 10, 2007Assignee: DNA Electronics LimitedInventors: Christofer Toumazou, Julius Georgiou
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Patent number: 7061300Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.Type: GrantFiled: February 27, 2001Date of Patent: June 13, 2006Assignee: STMicroelectronics S.r.l.Inventors: Valerio Pisati, Marco Cazzaniga, Alessandro Venca
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Patent number: 6424187Abstract: When a MOS transistor is turned off, a forward current flows into a diode connected to the MOS transistor. When the MOS transistor is conducted, a reverse bias is applied to the diode. When the MOS transistor is turned on during the reverse recovery time of the diode, a short-circuit current flows into the MOS transistor, the diode, and a battery connected in series with the diode and the MOS transistor. In this case, an overcurrent flows through the wiring of the battery momentarily, and electromagnetic wave generates from the wiring. Accordingly, noise caused by the electromagnetic wave is generated in an antenna to a radio receiver. The drain current of the MOS transistor is gradually increased by a delay circuit, and the MOS transistor is shifted from a completely turned-off state to a completely turned-on state with a time period longer than a reverse recovery time of the diode. Consequently, no reverse current flows through the diode.Type: GrantFiled: December 12, 1997Date of Patent: July 23, 2002Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Naoyuki Takahashi, Sakae Hikita, Keiichi Mashino
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Patent number: 6124739Abstract: A monolithically integrated signal processing circuit comprising a signal series branch connected between a signal input terminal and a signal output terminal; a reference potential terminal; a series capacitor inserted in serial manner in the signal series branch and having a parasitic capacitance acting like a capacitor that is connected between a first electrode of the series capacitor directed towards the signal input terminal and the reference voltage terminal; and a first parallel capacitor connected between the first electrode of the series capacitor and the reference potential terminal; with the first parallel capacitor being constituted at least in part by the parasitic capacitance.Type: GrantFiled: December 19, 1997Date of Patent: September 26, 2000Assignee: STMicroelectronics GmbHInventors: Gerhard Roither, Gunther Hackl, Uwe Fischer
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Patent number: 5757227Abstract: A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radio nuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification.Type: GrantFiled: August 12, 1996Date of Patent: May 26, 1998Assignee: The Regents of the University of CaliforniaInventors: James H. McQuaid, Anthony D. Lavietes
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Patent number: 5726593Abstract: A method and circuit in which one of at least two asynchronous constant frequency input clock signals is selected for being used as an output clock signal by use of a separate selection signal for providing redundancy for an asynchronous clock signal.Type: GrantFiled: November 22, 1996Date of Patent: March 10, 1998Assignee: Nokia Telecommunications OyInventor: Markku Ruuskanen
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Patent number: 5296763Abstract: A polar leapfrog filter includes at least one polar network. The polar network comprises a differentiator constituted by an operational amplifier having input and output terminals, and a first integrator formed by a first capacitor for providing negative feedback to the operational amplifier and a first variable transconductance amplifier; and a second integrator formed by a second capacitor for providing negative feedback to the first integrator, and a second variable transconductance amplifier. In the case where two or more said polar networks are incorporated, an integrator is provided between adjacent ones of the polar networks. The total number of all the circuits is selected to be odd and equal to the order of the filter. The adjacent ones of the circuits are connected in such a manner that leapfrog type negative feedback is effected.Type: GrantFiled: March 26, 1992Date of Patent: March 22, 1994Assignee: Toko, Inc.Inventors: Hiroshi Tanigawa, Hiroshi Kondo, Isao Fukai, Tsuneo Tohyama