Patents Examined by Tin Quach
  • Patent number: 4960723
    Abstract: An improved method for making a self-aligned vertical field effect transistor is provided wherein a nitride sidewall spacer is formed around a polysilicon gate, and an oxide sidewall spacer, which may be heavily doped with an n-type dopant, is formed covering the silicon nitride sidewall spacer. The silicon nitride sidewall spacer allows the oxide sidewall spacer of a conventional self-aligned vertical field effect transistor process to be removed partially or completely before making ohmic contact to the source thus increasing the contact area between the source and the source electrode and eliminating reliability problems related to n-type doped oxide in contact with aluminum electrodes.
    Type: Grant
    Filed: March 30, 1989
    Date of Patent: October 2, 1990
    Assignee: Motorola, Inc.
    Inventor: Robert B. Davies