Abstract: Methods and systems for performing semiconductor metrology directly on device structures are presented. A measurement model is created based on measured training data collected from at least one device structure. The trained measurement model is used to calculate process parameter values, structure parameter values, or both, directly from measurement data collected from device structures of other wafers. In some examples, measurement data from multiple targets is collected for model building, training, and measurement. In some examples, the use of measurement data associated with multiple targets eliminates, or significantly reduces, the effect of under layers in the measurement result, and enables more accurate measurements. Measurement data collected for model building, training, and measurement may be derived from measurements performed by a combination of multiple, different measurement techniques.

Abstract: This invention relates to a method for determining a wear state of a chisel, a chisel holder, and/or a chisel holder replacement system equipped with a chisel and chisel holder. For this method to give the user qualitative and quantitative information about the wear, according to one embodiment of this invention, a position of at least one point of the chisel and/or the chisel holder is determined by a contactless measurement method and a corresponding measurement result is compared in a switching unit to a reference value stored in a memory device.

Abstract: An electric arc detection device samples first, second and third filterings of a signal in a current window and in another window. A correlation is determined between first filtering samples of the current and the other window, a correlation is determined between second filtering samples of the current and the other window, and a correlation is determined between third filtering samples of the current window and the other window. An arc is then detected as a function of the correlations.

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

Abstract: Methods and systems for minimizing of algorithmic inaccuracy in scatterometry overlay (SCOL) metrology are provided. SCOL targets are designed to limit the number of oscillation frequencies in a functional dependency of a resulting SCOL signal on the offset and to reduce the effect of higher mode oscillation frequencies. The targets are segmented in a way that prevents constructive interference of high modes with significant amplitudes, and thus avoids the inaccuracy introduced by such terms into the SCOL signal. Computational methods remove residual errors in a semi-empirical iterative process of compensating for the residual errors algorithmically or through changes in target design.

Abstract: The present invention is concerned with a method of determining stationary signals for the diagnostics of an electromechanical systems in which electrical rotating machinery is used and in which at least one electrical or mechanical signal is measured during an operation of the electromechanical system. The method is used especially for condition monitoring of electric motors and generators. The method consists of measuring an analog waveform signal (S) of the electromechanical system and then manipulating that signal in various ways to obtain a frequencies spectrum, from which a vector of interest frequencies and corresponding vector of amplitudes are extracted to diagnose the electromechanical system.

Abstract: A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A velocity-compensated frequency sweeping interferometer has a single measurement light producing device that produces a coherent light source consisting of a single light beam. The light producing device produces a scanning wavelength light beam. A primary beam splitter produces a first reference beam and a first measurement beam from said single light beam. The first reference beam travels a fixed path length to a primary reference reflector and the first measurement beam travels to and from a moveable reflective target over an unknown path length. A distance measurement interferometer is created by interfering the first reference beam with the first measurement beam. A return frequency measurement interferometer provides a measure of frequency of the return beam from the target which, when compared with the frequency of the outgoing beam, allows for velocity compensation of the target.

Abstract: A method of operating a nonvolatile memory device that includes a three-dimensional (3D) memory cell array is provided as follows. A first read operation is performed on first memory cells connected to a first word line by using a first read voltage level. A read retry operation is, if the first read operation fails, performed on the first memory cells so that a read retry voltage level is set to a second read voltage level. A read offset table is determined based on a difference between the first read voltage level and the second read voltage level. The read offset table stores a plurality of read voltage offsets. A second read operation is performed on second memory cells connected to a second word line by using a third read voltage level determined using the read offset table.

Abstract: The invention relates to the use of distributed optical fiber sensors for distributed acoustic sensing, and in particular, modal analysis of distributed acoustic data obtained in-well to monitoring well integrity. By determining one or more acoustic modes corresponding to distributed speed of sound measurements within the wellbore, and analyzing variations in the distributed speed of sound measurement it is possible to derive information relating to a formation and/or fluid in the wellbore.

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract: Systems and methods for determining ion energy are described. One of the methods includes detecting output of a generator to identify a generator output complex voltage and current (V&I). The generator is coupled to an impedance matching circuit and the impedance matching circuit is coupled to an electrostatic chuck (ESC). The method further includes determining from the generator output complex V&I a projected complex V&I at a point along a path between an output of a model of the impedance matching circuit and a model of the ESC. The operation of determining of the projected complex V&I is performed using a model for at least part of the path. The method includes applying the projected complex V&I as an input to a function to map the projected complex V&I to a wafer bias value at the ESC model and determining an ion energy from the wafer bias value.

Abstract: A method for inspecting an object by ultrasound for detecting a wall thickness or defects of the object, wherein at least one ultrasonic pulse is transmitted into the object on a first position on an object's surface, the ultrasonic pulse is received on a second position on an object's surface possibly by propagating directly towards the second position along the surface or possibly as a result of reflection and/or diffractions of the pulse so that more than one pulse being received at different time and wherein a data signal is generated representing the received pulses and the associated moments in time wherein these pulses are received wherein the step is repeated for other positions and wherein the data signals are processed for generating processed signals to obtain a To FD image, wherein the processing for obtaining the processed data signals comprises at least three processing steps.

Abstract: The present invention extends to methods, systems, and computer program products for providing a matching system for correlating accelerometer data to known movements. Data representing known movements can be obtained and stored in a database such as by processing and storing accelerometer data obtained from one or more accelerometers worn by a user while performing a particular movement. The accelerometer data obtained from a particular movement can be processed to generate a feature set descriptive of the accelerations associated with a particular movement or series of movements.

Abstract: A system is provided for separating a plasma-containing fluid into separated plasma and a concentrated fluid. The system cooperates with a fluid flow circuit including a fluid separation chamber and a plasma outlet line associated therewith for removing separated plasma from the fluid separation chamber. The system includes an optical sensor assembly to monitor the contents of the plasma outlet line and produce an output indicative of the concentration of free plasma hemoglobin in the plasma outlet line. A controller of the system calculates the amount of free plasma hemoglobin in at least a portion of the concentrated fluid based at least in part on the output of the optical sensor assembly. The controller may periodically calibrate the optical sensor assembly by determining an instrument-specific correlation between optic output and free hemoglobin concentration and comparing it to experimentally determined data to ensure continued reliability of the optical sensor assembly.

Abstract: A memory device is provided which comprises an array of bitcells and a plurality of wordlines. Each bitcell of the array of bitcells is selectively coupled to a wordline of the plurality of wordlines and access to a selected bitcell of the array of bitcells requires an asserted voltage on a selected wordline with which the selected bitcell is associated. Read assist circuitry is provided, which is configured, when read access to the selected bitcell is carried out, to implement a reduction in the asserted voltage on the selected wordline, and wherein the read assist circuitry is configured to implement the reduction in the asserted voltage by selective connection of the selected wordline to a further wordline of the plurality of wordlines.

Abstract: A non-volatile memory includes a memory array and a controlling circuit. The memory array includes plural word lines and plural bit lines. The controlling circuit includes a processing circuit, a decoder, a driver, a timing controller and a sense amplifier. The decoder is connected with the processing circuit. The driver is connected with the decoder and the plural word lines. The timing controller is connected with the processing circuit. The sense amplifier is connected with the decoder, the timing controller and the plural word lines.